EP9315-CB Cirrus Logic Inc, EP9315-CB Datasheet - Page 7

• Manufacturer Part Number: EP9315-CB
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9315-CB

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, PCMCIA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 352-BGA
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: EDB9315A-Z
• For Use With: 598-1144 - KIT DEVELOPMENT EP9315 ARM9
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: No
• Other names: 598-1261

IDE Interface
The
connection to two AT Advanced Packet Interface (ATAPI)
compliant devices. The IDE port will attach to a master
and a slave device. The internal DMA controller performs
all data transfers using the Ultra DMA modes. The
interface supports the following operating modes:
•
•
Ethernet Media Access Controller (MAC)
The MAC subsystem is compliant with the ISO/TEC
802.3 topology for a single shared medium with several
stations. Multiple MII-compliant PHYs are supported.
Features include:
•
•
DS638PP4
DD[15-0]
IDEDA[2-0]
IDECSn[0,1]
DIORn
DIOWn
DMACKn
MDC
MDIO
RXCLK
MIIRXD[3:0]
RXDVAL
RXERR
TXCLK
MIITXD[3:0]
TXEN
TXERR
CRS
CLD
Table D. Ethernet Media Access Controller Pin Assignments
PIO Mode 0 thru 4
Ultra DMA Modes 0 thru 3
Supports 1/10/100 Mbps transfer rates for home /
small-business / large-business applications
Interfaces to an off-chip PHY through industry
standard Media Independent Interface (MII)
Pin Mnemonic
Pin Mnemonic
IDE
Table C. IDE Interface Pin Assignments
Interface
Management Data Clock
Management Data I/O
Receive Clock
Receive Data
Receive Data Valid
Receive Data Error
Transmit Clock
Transmit Data
Transmit Enable
Transmit Error
Carrier Sense
Collision Detect
provides
IDE Device address
IDE Chip Select 0 and 1
IDE Read Strobe
IDE Write Strobe
IDE DMA acknowledge
IDE Data bus
Pin Description
Pin Description
©
an
Copyright 2005 Cirrus Logic (All Rights Reserved)
industry-standard
Serial Interfaces (SPI, I
The SPI port can be configured as a master or a slave,
supporting the National Semiconductor
Texas Instruments
The AC'97 port supports multiple codecs for multichannel
audio output with a single stereo input. Three I
can be configured to support six channel 24-bit audio.
These ports are multiplexed so that I
over either the AC'97 pins or the SPI pins. The second
and third I2S ports' serial input and serial output pins are
multiplexed with EGPIO[4,5,6,13]. The clocks supplied in
the first I2S port are also used for the second and third
I2S ports.
•
•
•
Raster / LCD Interface
The Raster / LCD interface provides data and interface
signals for a variety of display types. It features fully
programmable video interface timing for non-interlaced
flat panel or dual scan displays. Resolutions up to
1024 x 768 are supported from a unified SDRAM based
frame buffer. A 16-bit PWM provides control for LCD
panel contrast. LCD specific features include:
SCLK1
SFRM1
SSPRX1 SPI Serial Input
SSPTX1
ARSTn
ABITCLK AC'97 Bit Clock
ASYNC
ASDI
ASDO
Name
Pin
Normal Mode: One SPI Port and one AC’97 Port
I
Ports
I
Ports
2
2
S on SSP Mode: One AC’97 Port and up to three I
S on AC’97 Mode: One SPI Port and up to three I
SPI Bit Clock
SPI Frame Clock I2S Frame Clock
SPI Serial
Output
AC'97 Reset
AC'97 Frame
Clock
AC'97 Serial
Input
AC'97 Serial
Output
Normal Mode
Description
Table E. Audio Interfaces Pin Assignment
Enhanced Universal Platform SOC Processor
Pin
®
signaling protocols.
I2S Serial Clock
I2S Serial Input
I2S Serial Output
(No I2S Master
Clock)
AC'97 Reset
AC'97 Bit Clock
AC'97 Frame
Clock
AC'97 Serial Input I2S Serial Input
AC'97 Serial
Output
Pin Description Pin Description
I2S on SSP
Mode
2
S and AC ’97)
2
S port 0 will take
®
SPI Bit Clock
SPI Frame Clock
SPI Serial Input
SPI Serial Output
I2S Master Clock
I2S Serial Clock
I2S Frame Clock
I2S Serial Output
, Motorola
I2S on AC'97
Mode
2
S ports
EP9315
®
and
2
2
S
S
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