EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 155

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

VidClkDiv
DS785UM1
VENA
31
15
Address:
Default:
Definition:
Bit Descriptions:
ESEL
30
14
PSEL
29
13
28
12
SWRST:
0x8093_0084 - Read/Write, Software locked
0x0000_0000
Configures video clock for the raster engine. Selects input to VCLK dividers
from either PLL1 or PLL2, and defines a programmable divide value.
RSVD:
VENA:
ESEL:
PSEL:
PDIV:
VDIV:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Software reset. A one to zero transition of this bit initiates
a software reset.
Reserved. Unknown During Read.
Enable VCLK divider.
External clock source select.
0 - use the external XTALI clock input as the clock source.
1 - use one of the internal PLLs selected by PSEL as the
clock source.
PLL source select.
1 - select PLL2 as the clock source.
0 - select PLL1 as the clock source.
Pre-divider value. Generates divide by 2, 2.5, or 3 from the
clock source.
00 - Disable clock
01 - Divide-by-2
10 - Divide-by-2.5
11 - Divide-by-3
VCLK divider value. Forms a divide-by-N of the pre-divide
clock output. VCLK is the source clock divided by PDIV
divided by N. Must be at least two.
PDIV
24
8
RSVD
RSVD
23
7
22
6
21
5
20
4
VDIV
19
3
EP93xx User’s Guide
System Controller
18
2
17
1
16
5-29
0
5