EP9312-IBZ Cirrus Logic Inc, EP9312-IBZ Datasheet - Page 406

• Manufacturer Part Number: EP9312-IBZ
• Description: IC ARM920T MCU 200MHZ 352-PBGA
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9312-IBZ

• Core Size: 16/32-Bit
• Package / Case: 352-BGA
• Core Processor: ARM9
• Speed: 200MHz
• Connectivity: EBI/EMI, EIDE, Ethernet, I²C, IrDA, Keypad/Touchscreen, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LCD, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 8x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Controller Family/series: (ARM9)
• A/d Converter: 12 Bits
• No. Of I/o Pins: 65
• Clock Frequency: 200MHz
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1260

10
10-12
10.1.10.1.5 DMA_BWC_WAIT
10.1.10.2.1 DMA_NO_BUF
10.1.10.2.2 DMA_BUF_ON
DMA Controller
EP93xx User’s Guide
10.1.10.2 M2M Buffer Control Finite State Machine
The DMA M2M Control FSM enters the DMA_BWC_WAIT state when the byte count is within
15 bytes of a multiple of the BWC value.
The DMA M2M Control FSM stays in this state for one cycle only.
The DMA M2M Buffer FSM resets to the DMA_NO_BUF state. This state reflects that no
buffer descriptor has as yet been programmed in the DMA controller.
The DMA M2M Buffer FSM exits this state when one of the BCRx (x = 0 or 1) registers is
programmed. If BCR0 is written to, then the FSM moves to the DMA_BUF_ON state and
buffer0 becomes the active buffer available for a transfer. If BCR1 is written to then the FSM
moves to the DMA_BUF_ON state and buffer1 becomes the active buffer available for a
transfer.
The DMA Buffer FSM enters the DMA_BUF_ON state from the DMA_NO_BUF state when
one of the BCRx registers is written to.
The DMA Buffer FSM enters the DMA_BUF_ON state from the DMA_BUF_NEXT state when
the transfer from the active buffer has ended. This end-of-buffer can be due to the BCRx
register value reaching zero, or receipt of a DEOT input from the external device (when in
external DMA transfer mode and DEOT is configured as an input signal to the DMA).
Data transfers to or from memory or external bus can occur in the DMA_BUF_ON state.
When the DMA Buffer FSM transitions from DMA_BUF_NEXT to DMA_BUF_ON state, the
NFB (Next Frame Buffer) interrupt is generated. This signals to software that rollover is
occurring to the other buffer and also that one of the BCRx registers is now free for update
DMA_BUF_NEXT
Figure 10-3. M2M DMA Buffer Finite State Machine
BCRx_WRITE(x = 1 or 0)
DMA_NO_BUF
Copyright 2007 Cirrus Logic
Buffer End
Buffer End
DMA_BUF_ON
BCRx_WRITE (x = 0 or 1)
DS785UM1