ATMEGA16A-AUR Atmel, ATMEGA16A-AUR Datasheet - Page 148

• Manufacturer Part Number: ATMEGA16A-AUR
• Description: MCU AVR 16KB FLASH 16MHZ 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16A-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.2.1
19.3
148
Clock Generation
ATmega16A
AVR USART vs. AVR UART – Compatibility
The USART is fully compatible with the AVR UART regarding:
However, the receive buffering has two improvements that will affect the compatibility in some
special cases:
The following control bits have changed name, but have same functionality and register location:
The clock generation logic generates the base clock for the Transmitter and Receiver. The
USART supports four modes of clock operation: Normal Asynchronous, Double Speed Asyn-
chronous, Master Synchronous and Slave Synchronous mode. The UMSEL bit in USART
Control and Status Register C (UCSRC) selects between asynchronous and synchronous oper-
ation. Double Speed (Asynchronous mode only) is controlled by the U2X found in the UCSRA
Register. When using Synchronous mode (UMSEL = 1), the Data Direction Register for the XCK
pin (DDR_XCK) controls whether the clock source is internal (Master mode) or external (Slave
mode). The XCK pin is only active when using Synchronous mode.
Figure 19-2
• Bit locations inside all USART Registers
• Baud Rate Generation
• Transmitter Operation
• Transmit Buffer Functionality
• Receiver Operation
• A second Buffer Register has been added. The two Buffer Registers operate as a circular
• The receiver Shift Register can now act as a third buffer level. This is done by allowing the
• CHR9 is changed to UCSZ2
• OR is changed to DOR
FIFO buffer. Therefore the UDR must only be read once for each incoming data! More
important is the fact that the Error Flags (FE and DOR) and the 9th data bit (RXB8) are
buffered with the data in the receive buffer. Therefore the status bits must always be read
before the UDR Register is read. Otherwise the error status will be lost since the buffer state
is lost.
received data to remain in the serial Shift Register (see
are full, until a new start bit is detected. The USART is therefore more resistant to Data
OverRun (DOR) error conditions.
shows a block diagram of the clock generation logic.
Figure
19-1) if the Buffer Registers
8154B–AVR–07/09