ATMEGA16A-AUR Atmel, ATMEGA16A-AUR Datasheet - Page 151

• Manufacturer Part Number: ATMEGA16A-AUR
• Description: MCU AVR 16KB FLASH 16MHZ 44TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA16A-AUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 32
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

19.4
8154B–AVR–07/09
Frame Formats
Figure 19-3. Synchronous Mode XCK Timing.
The UCPOL bit UCRSC selects which XCK clock edge is used for data sampling and which is
used for data change. As
rising XCK edge and sampled at falling XCK edge. If UCPOL is set, the data will be changed at
falling XCK edge and sampled at rising XCK edge.
A serial frame is defined to be one character of data bits with synchronization bits (start and stop
bits), and optionally a parity bit for error checking. The USART accepts all 30 combinations of
the following as valid frame formats:
A frame starts with the start bit followed by the least significant data bit. Then the next data bits,
up to a total of nine, are succeeding, ending with the most significant bit. If enabled, the parity bit
is inserted after the data bits, before the stop bits. When a complete frame is transmitted, it can
be directly followed by a new frame, or the communication line can be set to an idle (high) state.
Figure 19-4
optional.
Figure 19-4. Frame Formats
be
• 1 start bit
• 5, 6, 7, 8, or 9 data bits
• no, even or odd parity bit
• 1 or 2 stop bits
St
(n)
P
Sp
IDLE
(IDLE)
UCPOL = 1
UCPOL = 0
illustrates the possible combinations of the frame formats. Bits inside brackets are
St
RxD / TxD
RxD / TxD
0
Start bit, always low.
Data bits (0 to 8).
Parity bit. Can be odd or even.
Stop bit, always high.
No transfers on the communication line (RxD or TxD). An IDLE line must
high.
XCK
XCK
Figure 19-3
1
2
3
shows, when UCPOL is zero the data will be changed at
4
FRAME
[5]
[6]
[7]
[8]
Sample
Sample
[P]
Sp1 [Sp2] (St / IDLE)
ATmega16A
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