PIC16F87-I/ML Microchip Technology, PIC16F87-I/ML Datasheet - Page 107

• Manufacturer Part Number: PIC16F87-I/ML
• Description: IC MCU FLASH 4KX14 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F87-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 368Byte
• Cpu Speed: 20MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNAC164033 - ADAPTER 28QFN TO 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Data Converters: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

When setting up an asynchronous reception, follow
these steps:
1.
2.
3.
4.
5.
TABLE 11-8:
 2005 Microchip Technology Inc.
0Bh, 8Bh,
10Bh,18Bh
0Ch
18h
1Ah
8Ch
98h
99h
Legend:
Note 1:
Address
Initialize the SPBRG register for the appropriate
baud rate. If a high-speed baud rate is desired,
set bit BRGH (Section 11.1 “AUSART Baud
Rate Generator (BRG)”).
Enable the asynchronous serial port by clearing
bit SYNC and setting bit SPEN.
If interrupts are desired, then set enable bit
RCIE.
If 9-bit reception is desired, then set bit RX9.
Enable the reception by setting bit CREN.
x = unknown, - = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
This bit is only implemented on the PIC16F88. The bit will read ‘0’ on the PIC16F87.
INTCON
PIR1
RCSTA
RCREG AUSART Receive Data Register
PIE1
TXSTA
SPBRG Baud Rate Generator Register
Name
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
CSRC
SPEN
Bit 7
GIE
—
—
ADIE
ADIF
PEIE
Bit 6
RX9
TX9
(1)
(1)
TMR0IE INT0IE
SREN
TXEN
RCIE
RCIF
Bit 5
CREN ADDEN
SYNC
TXIF
TXIE
Bit 4
SSPIF
SSPIE
RBIE
Bit 3
—
6.
7.
8.
9.
10. If using interrupts, ensure that GIE and PEIE
TMR0IF
CCP1IF TMR2IF TMR1IF
CCP1IE TMR2IE TMR1IE
BRGH
FERR
Bit 2
Flag bit RCIF will be set when reception is com-
plete and an interrupt will be generated if enable
bit RCIE is set.
Read the RCSTA register to get the ninth bit (if
enabled) and determine if any error occurred
during reception.
Read the 8-bit received data by reading the
RCREG register.
If any error occurred, clear the error by clearing
enable bit CREN.
(bits 7 and 6) of the INTCON register are set.
INT0IF
OERR
TRMT
Bit 1
RX9D
TX9D
RBIF
Bit 0
PIC16F87/88
0000 000x
-000 0000
0000 000x
0000 0000
-000 0000
0000 -010
0000 0000
POR, BOR
Value on:
DS30487C-page 105
0000 000u
-000 0000
0000 000x
0000 0000
-000 0000
0000 -010
0000 0000
Value on
all other
Resets