PIC16F87-I/ML Microchip Technology, PIC16F87-I/ML Datasheet - Page 140

• Manufacturer Part Number: PIC16F87-I/ML
• Description: IC MCU FLASH 4KX14 EEPROM 28QFN
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F87-I/ML

• Core Size: 8-Bit
• Program Memory Size: 7KB (4K x 14)
• Oscillator Type: Internal
• Core Processor: PIC
• Speed: 20MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 368 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Controller Family/series: PIC16F
• No. Of I/o's: 16
• Eeprom Memory Size: 256Byte
• Ram Memory Size: 368Byte
• Cpu Speed: 20MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT28QFN3 - SOCKET TRAN ICE 18DIP/28QFNAC164322 - MODULE SOCKET MPLAB PM3 28/44QFNAC164033 - ADAPTER 28QFN TO 18DIPDV007003 - PROGRAMMER UNIVERSAL PROMATE II
• Data Converters: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC16F87/88
FIGURE 15-6:
15.10 Interrupts
The PIC16F87/88 has up to 12 sources of interrupt.
The Interrupt Control register (INTCON) records
individual interrupt requests in flag bits. It also has
individual and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>),
enables (if set) all unmasked interrupts, or disables (if
cleared) all interrupts. When bit GIE is enabled and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be
disabled through their corresponding enable bits in
various registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on Reset.
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine, as well as sets the GIE bit which
re-enables interrupts.
DS30487C-page 138
Note:
INTERNAL RESET
PWRT TIME-OUT
INTERNAL POR
OST TIME-OUT
Individual interrupt flag bits are set
regardless
corresponding mask bit or the GIE bit.
MCLR
V
DD
SLOW RISE TIME (MCLR TIED TO V
of
the
status
0V
T
PWRT
of
their
1V
5V
The RB0/INT pin interrupt, the RB port change interrupt
and the TMR0 overflow interrupt flags are contained in
the INTCON register.
The peripheral interrupt flags are contained in the
Special Function Register, PIR1. The corresponding
interrupt enable bits are contained in Special Function
Register, PIE1 and the peripheral interrupt enable bit is
contained in Special Function Register, INTCON.
When an interrupt is serviced, the GIE bit is cleared to
disable any further interrupt, the return address is
pushed onto the stack and the PC is loaded with 0004h.
Once in the Interrupt Service Routine, the source(s) of
the interrupt can be determined by polling the interrupt
flag bits. The interrupt flag bit(s) must be cleared in
software before re-enabling interrupts to avoid
recursive interrupts.
For external interrupt events, such as the INT pin or
PORTB change interrupt, the interrupt latency will be
three or four instruction cycles. The exact latency
depends on when the interrupt event occurs, relative to
the current Q cycle. The latency is the same for one or
two cycle instructions. Individual interrupt flag bits are
set regardless of the status of their corresponding
mask bit, PEIE bit or the GIE bit.
DD
THROUGH RC NETWORK)
T
OST
 2005 Microchip Technology Inc.