ATMEGA645-16MU Atmel, ATMEGA645-16MU Datasheet - Page 195

• Manufacturer Part Number: ATMEGA645-16MU
• Description: IC AVR MCU FLASH 64K 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA645-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, UART, USI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2570M–AVR–04/11
Table 20-1.
Note:
USIWM1
0
0
1
1
1. The DI and USCK pins are renamed to Serial Data (SDA) and Serial Clock (SCL) respectively
to avoid confusion between the modes of operation.
USIWM0
Relations between USIWM1..0 and the USI Operation
0
1
0
1
Description
Outputs, clock hold, and start detector disabled. Port pins operates as
normal.
Three-wire mode. Uses DO, DI, and USCK pins.
The Data Output (DO) pin overrides the corresponding bit in the PORT
Register in this mode. However, the corresponding DDR bit still
controls the data direction. When the port pin is set as input the pins
pull-up is controlled by the PORT bit.
The Data Input (DI) and Serial Clock (USCK) pins do not affect the
normal port operation. When operating as master, clock pulses are
software generated by toggling the PORT Register, while the data
direction is set to output. The USITC bit in the USICR Register can be
used for this purpose.
Two-wire mode. Uses SDA (DI) and SCL (USCK) pins
The Serial Data (SDA) and the Serial Clock (SCL) pins are bi-
directional and uses open-collector output drives. The output drivers
are enabled by setting the corresponding bit for SDA and SCL in the
DDR Register.
When the output driver is enabled for the SDA pin, the output driver will
force the line SDA low if the output of the Shift Register or the
corresponding bit in the PORT Register is zero. Otherwise the SDA
line will not be driven (i.e., it is released). When the SCL pin output
driver is enabled the SCL line will be forced low if the corresponding bit
in the PORT Register is zero, or by the start detector. Otherwise the
SCL line will not be driven.
The SCL line is held low when a start detector detects a start condition
and the output is enabled. Clearing the Start Condition Flag (USISIF)
releases the line. The SDA and SCL pin inputs is not affected by
enabling this mode. Pull-ups on the SDA and SCL port pin are
disabled in Two-wire mode.
Two-wire mode. Uses SDA and SCL pins.
Same operation as for the Two-wire mode described above, except
that the SCL line is also held low when a counter overflow occurs, and
is held low until the Counter Overflow Flag (USIOIF) is cleared.
ATmega325/3250/645/6450
(1)
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