ATMEGA645-16MU Atmel, ATMEGA645-16MU Datasheet - Page 267

• Manufacturer Part Number: ATMEGA645-16MU
• Description: IC AVR MCU FLASH 64K 64-QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA645-16MU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 53
• Program Memory Size: 64KB (32K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-MLF®, 64-QFN
• Processor Series: ATMEGA64x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 4 KB
• Interface Type: SPI, UART, USI
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Operating Supply Voltage: 2.7 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: EWAVR, EWAVR-BL
• Development Tools By Supplier: ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Package: 64MLF EP
• Device Core: AVR
• Family Name: ATmega
• Maximum Speed: 16 MHz
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAGATAVRISP2 - PROGRAMMER AVR IN SYSTEM
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

2570M–AVR–04/11
Table 26-4.
Note:
Table 26-5.
Note:
Fuse High Byte
OCDEN
JTAGEN
SPIEN
WDTON
EESAVE
BOOTSZ1
BOOTSZ0
BOOTRST
Fuse Low Byte
CKDIV8
CKOUT
SUT1
SUT0
CKSEL3
CKSEL2
CKSEL1
CKSEL0
(1)
1. The SPIEN Fuse is not accessible in serial programming mode.
2. The default value of BOOTSZ1..0 results in maximum Boot Size. See
3. See
4. Never ship a product with the OCDEN Fuse programmed regardless of the setting of Lock bits
5. If the JTAG interface is left unconnected, the JTAGEN fuse should if possible be disabled. This
1. The default value of SUT1..0 results in maximum start-up time for the default clock source.
2. The default setting of CKSEL3..0 results in internal RC Oscillator @ 8 MHz. See
3. The CKOUT Fuse allow the system clock to be output on PORTE7. See
4. See
(3)
(4)
(4)
(3)
(5)
for details.
and JTAGEN Fuse. A programmed OCDEN Fuse enables some parts of the clock system to
be running in all sleep modes. This may increase the power consumption.
to avoid static current at the TDO pin in the JTAG interface.
See
page 29
on page 31
Fuse High Byte
Fuse Low Byte
“Register Description” on page 47
Table 27-4 on page 301
“System Clock Prescaler” on page 32
for details.
for details.
Bit No
7
6
5
4
3
2
1
0
Bit No
7
6
5
4
3
2
1
0
Description
Enable OCD
Enable JTAG
Enable Serial Program and Data
Downloading
Watchdog Timer always on
EEPROM memory is preserved
through the Chip Erase
Select Boot Size (see
for details)
Select Boot Size (see
for details)
Select Reset Vector
Description
Divide clock by 8
Clock output
Select start-up time
Select start-up time
Select Clock source
Select Clock source
Select Clock source
Select Clock source
for details.
ATmega325/3250/645/6450
for details.
for details.
Table 26-6
Table 26-6
Default Value
1 (unprogrammed,
OCD disabled)
0 (programmed, JTAG
enabled)
0 (programmed, SPI
prog. enabled)
1 (unprogrammed)
1 (unprogrammed,
EEPROM not
preserved)
0 (programmed)
0 (programmed)
1 (unprogrammed)
Default Value
0 (programmed)
1 (unprogrammed)
1 (unprogrammed)
0 (programmed)
0 (programmed)
0 (programmed)
1 (unprogrammed)
0 (programmed)
Table 25-6 on page 262
“Clock Output Buffer”
(2)
(2)
(1)
(2)
(2)
(2)
(1)
(2)
Table 8-5 on
267