DSPIC30F2020-30I/SP Microchip Technology, DSPIC30F2020-30I/SP Datasheet - Page 10

• Manufacturer Part Number: DSPIC30F2020-30I/SP
• Description: IC DSPIC MCU/DSP 12K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2020-30I/SP

• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC30F1010/202X
13. Module: ADC
14. Module: ADC
15. Module: ADC
DS80445D-page 10
The dedicated ADC sample-and-hold circuits can
be triggered by signals from the PWM module. The
dsPIC30F1010/202X data sheet indicates that the
resolution of the PWM to ADC sample-and-hold
trigger timing is 8 ns. The existing implementation
has a 41.6 ns resolution. In other words, when the
PWM to ADC trigger is fired, an ADC sample may
occur 1 ns to 41.6 ns later.
Work around
None.
Affected Silicon Revisions
The dsPIC30F1010/202X data sheet specifies that
each ADC pin pair has its own interrupt vector.
These
dsPIC30F1010/202X devices.
Work around
Each ADC pin pair can be configured to initiate a
global ADC interrupt by setting the corresponding
IRQENx bit in the ADCPCx register. The ADBASE
register can be used to create a jump table in the
global ADC interrupt which will execute the
appropriate ADC service routine for a particular
ADC pin pair. There is an ADBASE register code
example in the dsPIC30F1010/202X data sheet
which illustrates using the ADBASE register in this
way.
Affected Silicon Revisions
The data sheet indicates that the conversion rate
for the ADC module is 2.0 Msps. The ADC module
on
maximum conversion rate of 1.5 Msps.
Work around
None.
Affected Silicon Revisions
A1
A1
A1
X
X
X
the
A2
A2
A2
X
X
X
interrupts
dsPIC30F1010/202X
A3
A3
A3
X
X
X
do
not
work
silicon
on
has
the
a
16. Module: ADC
17. Module: Output Compare
In the dsPIC30F202X device, the ADC inputs that
do not have a dedicated sample-and-hold circuit
will yield inaccurate conversion results unless the
work around is implemented. The channels
included are AN1, AN3, AN5, AN7, AN8, AN9,
AN10 and AN11 (depending on the package
variant). In the dsPIC30F1010 device, all of the
channels mentioned above are included, plus AN4
and AN6.
Work around
In the ADCON register, configure the ADC with
Order = 0 and SEQSAMP = 1. This configuration
allows for accurate conversion of the analog
channels which use the shared sample-and-hold
circuit. The exception to this is the RB7 pin and all
multiplexed functions (refer to silicon issue
number 46.).
Affected Silicon Revisions
A glitch will be produced on an output compare pin
under the following conditions:
• The user software initially drives the I/O pin
• The output compare module is configured and
When these events occur, the output compare
module will drive the pin low for one instruction
cycle (T
Work around
None. However, the user may use a timer inter-
rupt, and write to the associated PORT register
to control the pin manually.
Affected Silicon Revisions
A1
A1
X
high using the output compare module or a
write to the associated PORT register.
enabled to drive the pin low at some later time
(OCxCON = 0x0002 or OCxCON = 0x0003).
X
CY
A2
A2
X
X
) after the module is enabled.
A3
A3
X
X
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