DSPIC30F2020-30I/SP Microchip Technology, DSPIC30F2020-30I/SP Datasheet - Page 3

• Manufacturer Part Number: DSPIC30F2020-30I/SP
• Description: IC DSPIC MCU/DSP 12K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2020-30I/SP

• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

TABLE 2:
© 2010 Microchip Technology Inc.
Note 1:
Compare
Compare
Compare
Module
Output
Output
Output
UART
UART
UART
UART
UART
UART
UART
UART
UART
UART
UART
I
2
SPI
SPI
SPI
SPI
C™
Only those issues indicated in the last column apply to the current silicon revision.
SILICON ISSUE SUMMARY (CONTINUED)
Frame Master
Master Mode
Bus Collision
Match Mode
Slave Select
IrDA
PWM Mode
High-Speed
High-Speed
High-Speed
Baud Rate
Auto-Baud
Auto-Baud
IrDA Mode
FIFO Error
Generator
Operation
Compare
Feature
Receive
Mode
Mode
Mode
Mode
Mode
Flags
Dual
®
—
—
—
Mode
Number
Item
29.
31.
17.
18.
19.
20.
21.
22.
23.
24.
25.
26.
27.
28.
30.
32.
33.
34.
35.
The output compare module produces a glitch on the
output when an I/O pin is initially set high and the
module is configured to drive the pin low at a specified
time.
The output compare module will miss one compare
event when the duty cycle register value is updated
from 0x0000 to 0x0001.
In Dual Compare Match mode, the OCx output is not
reset when the OCxR and OCxRS registers are loaded
with values having a difference of 1.
The SPI module slave select functionality will not work
correctly.
The SPI module will fail to generate frame synchronization
pulses in Frame Master mode if FRMDLY = 1.
The SMP bit does not have any effect when the SPI
module is configured for a 1:1 prescale factor in Master
mode.
The SPIxCON1 DISSCK bit does not influence port
functionality.
If the Baud Rate Generator register (BRG) contains an
odd value and the parity option is enabled, the module
may falsely indicate parity errors.
The Receive Buffer Overrun Error Status bit may be set
prematurely.
UART receptions may be corrupted in High Baud Rate
mode (BRGH = 1).
UTXISEL0 bit in the UxSTA register is always read as
zero regardless of the value written to it.
The auto-baud feature does not work properly in High
Baud Rate mode (BRGH = 1).
When the auto-baud feature is enabled, the Sync
Break character (0x55) may be loaded into the FIFO as
data.
The operation of the RXINV bit in the UxMODE register
is inverted.
The auto-baud feature measures baud rate inaccurately
for certain baud rate and clock speed combinations.
The 16x baud clock signal on the BCLK pin is present
only when the module is transmitting.
When the UART is in 4x mode (BRGH = 1) and using
two Stop bits (STSEL = 1), it may sample the first Stop
bit instead of the second one.
Under certain circumstances, the PERR and FERR
error bits may not be correct for all bytes in the receive
FIFO.
The Bus Collision Status bit does not get set when a
bus collision occurs during a Restart or Stop event.
Issue Summary
dsPIC30F1010/202X
DS80445D-page 3
A1
Revisions
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Affected
A2
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
(1)
A3
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X