DSPIC30F2020-30I/SP Microchip Technology, DSPIC30F2020-30I/SP Datasheet - Page 9

• Manufacturer Part Number: DSPIC30F2020-30I/SP
• Description: IC DSPIC MCU/DSP 12K 28DIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F2020-30I/SP

• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 21
• Program Memory Size: 12KB (4K x 24)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE4000, DM240002, DM300027, DM330011, DM300018, DM183021
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM300023 - KIT DEMO DSPICDEM SMPS BUCKDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

11. Module: PWM
© 2010 Microchip Technology Inc.
Setting the XPRES bit in the PWMCONx register
should enable a current-limit source to reset the
PWM period in Independent Time Base mode.
This mode is not functioning correctly.
If the selected current-limit signal (either an analog
comparator or external signal) triggers after the
falling edge of PWMH, then the XPRES operation
functions correctly. The PWM deasserted time is
truncated and the PWM period is terminated early,
and a new PWM cycle begins.
If the selected current-limit signal (either an analog
comparator or external signal) triggers before the
falling edge of PWMH, the PWMH asserted time is
truncated, and the inactive time after the falling
edge PWMH remains constant.
The proper XPRES behavior is to ignore the
current-limit signal until the falling edge of the
PWM period.
This issue may not be a problem in applications
that control inductor current above a specified
minimum current level. When the inductor current
falls below the specified minimum value during the
PWMH off-time, the PWM period is truncated and
a new cycle begins to increase the inductor
current.
Work around
None.
Affected Silicon Revisions
A1
X
A2
X
A3
X
12. Module: ADC
dsPIC30F1010/202X
In order to perform multiple analog-to-digital
conversions using the global software trigger, the
PxRDY bits in the ADSTAT register must be
cleared. The data sheet indicates that the user can
configure the ADC pin pairs to perform a
conversion when the GSWTRG bit in the ADCON
register is set. When the conversion is available,
the user must then clear the GSWTRG bit and set
it again to perform another conversion. Contrary to
what the data sheet indicates, this will not initiate
another conversion unless the PxRDY bits are
cleared. Clearing the PxRDY bits automatically
clears the GSWTRG bit.
This only applies to a polling-based approach. If an
interrupt-based approach is used, the user is
required to clear the PxRDY bits in the ADC
Interrupt Service Routine (ISR).
Work around
The following sequence should be followed to
manually trigger ADC conversions using the global
software trigger (polling-based only.)
1. Set the GSWTRG bit in ADCON to initiate a
2. Check the PxRDY bits to determine when the
3. Clear the PxRDY bits. The GSWTRG bit will be
4. Repeat steps 1 through 3 to perform additional
Alternately, the individual software trigger can be
selected by setting the TRGSRCx<5:0> bits in the
ADCPCx register equal to 0x01. Instead of using
the global software trigger, the individual software
trigger bits (ADCPCx<SWTRGx>) can be used to
trigger a conversion on a given analog pin pair. In
a bit-polling approach, the PENDx in the ADCPCx
register should be used to determine when a
conversion is completed. In an interrupt-based
approach, the PxRDY bits get set when the
conversion is complete. These bits must be
cleared in the ADC Interrupt Service Routine in
order to enable future interrupts.
Affected Silicon Revisions
A1
X
conversion on channels which have the trigger
source as the global software trigger (via the
TRGSRCx<5:0>
registers).
conversion(s) is completed.
cleared as a result of this operation.
conversions.
A2
X
A3
X
bits
in
DS80445D-page 9
the
ADCPCx