PIC16F877-04E/PT Microchip Technology, PIC16F877-04E/PT Datasheet - Page 333

IC MCU FLASH 8KX14 EE 44TQFP

PIC16F877-04E/PT

Manufacturer Part Number
PIC16F877-04E/PT
Description
IC MCU FLASH 8KX14 EE 44TQFP
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16F877-04E/PT

Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
33
Program Memory Size
14KB (8K x 14)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
368 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 125°C
Package / Case
44-TQFP, 44-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
PIC16F87704E/PT

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16F877-04E/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
17.6
17.6.1
1997 Microchip Technology Inc.
Master SSP Module / Basic SSP Module Compatibility
Initialization
Example 17-2:
When changing from the SPI in the Basic SSP module, the SSPSTAT register contains two addi-
tional control bits. These bits are:
• SMP, SPI data input sample phase
• CKE, SPI Clock Edge Select
To be compatible with the SPI of the Master SSP module, these bits must be appropriately con-
figured. If these bits are not at the states shown in
occur.
Table 17-4: New bit States for Compatibility
Basic SSP Module
CLRF
CLRF
BSF
MOVLW
MOVWF
BSF
BSF
BCF
BSF
MOVLW
MOVWF
CKP
1
0
STATUS
SSPSTAT
SSPSTAT, CKE ; CKE = 1
0x31
SSPCON
STATUS, RP0
PIE, SSPIE
STATUS, RP0
INTCON, GIE
DataByte
SSPBUF
SPI Master Mode Initialization
Preliminary
CKP
; Bank 0
; SMP = 0, CKE = 0, and clear status bits
; Set up SPI port, Master mode, CLK/16,
;
;
; Bank 1
; Enable SSP interrupt
; Bank 0
; Enable, enabled interrupts
; Data to be Transmitted
;
; Start Transmission
1
0
Data xmit on falling edge (CKE=1 & CKP=1)
Data sampled in middle (SMP=0 & Master mode)
Could move data from RAM location
Master SSP Module
CKE
0
0
Section 17. MSSP
Table
17-4, improper SPI communication may
SMP
0
0
DS31017A-page 17-57
17

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