AT91SAM9G10-CU Atmel, AT91SAM9G10-CU Datasheet - Page 14

• Manufacturer Part Number: AT91SAM9G10-CU
• Description: IC MCU ARM9 SAMPLING 217CBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM9G10-CU

• Core Processor: ARM9
• Core Size: 16/32-Bit
• Speed: 266MHz
• Connectivity: EBI/EMI, I²C, IrDA, ISI, MMC, SPI, SSC, UART/USART, USB
• Peripherals: DMA, LCD, POR, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: ROM
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 1.08 V ~ 1.32 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 217-LFBGA
• Controller Family/series: AT91
• No. Of I/o's: 96
• Ram Memory Size: 16KB
• Cpu Speed: 266MHz
• No. Of Timers: 1
• Rohs Compliant: Yes
• Processor Series: AT91SAMx
• Core: ARM926EJ-S
• Data Bus Width: 32 bit
• Data Ram Size: 16 KB
• Interface Type: EBI, SPI, TWI, USART
• Maximum Clock Frequency: 266 MHz
• Number Of Programmable I/os: 96
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM9G10-EK
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

7.2
7.3
7.4
14
Debug and Test Features
Bus Matrix
Peripheral DMA Controller
AT91SAM9G10
• Integrated Embedded In-circuit Emulator Real-Time
• Debug Unit
• IEEE1149.1 JTAG Boundary-scan on All Digital Pins
• Five Masters and Five Slaves handled
• One Address Decoder Provided per Master
• Boot Mode Select Option
• Remap Command
• Transfers from/to peripheral to/from any memory space without intervention of the processor.
• Next Pointer Support, forbids strong real-time constraints on buffer management.
• Nineteen channels
– Two real-time Watchpoint Units
– Two Independent Registers: Debug Control Register and Debug Status Register
– Test Access Port Accessible through JTAG Protocol
– Debug Communications Channel
– Two-pin UART
– Debug Communication Channel Interrupt Handling
– Chip ID Register
– Handles Requests from the ARM926EJ-S, USB Host Port, LCD Controller and the
– Round-Robin Arbitration (three modes supported: no default master, last accessed
– Burst Breaking with Slot Cycle Limit
– Three different slaves may be assigned to each decoded memory area: one for
– Non-volatile Boot Memory can be Internal or External.
– Selection is made by BMS pin sampled at reset.
– Allows Remapping of an Internal SRAM in Place of the Boot Non-Volatile Memory
– Allows Handling of Dynamic Exception Vectors
– Two for each USART
– Two for the Debug Unit
– Two for each Serial Synchronous Controller
– Two for each Serial Peripheral Interface
– One for the Multimedia Card Interface
Peripheral DMA Controller to internal ROM, internal SRAM, EBI, APB, LCD
Controller and USB Host Port.
default master, fixed default master)
internal boot, one for external boot, one after remap.
6462AS–ATARM–03-Jun-09