ATMEGA644P-A15MZ Atmel, ATMEGA644P-A15MZ Datasheet - Page 186

• Manufacturer Part Number: ATMEGA644P-A15MZ
• Description: MCU AVR 64KB FLASH 16MHZ 44QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA644P-A15MZ

• Package / Case: 44-VQFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 32
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: I²C, SPI, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

17.9.1
17.9.2
186
ATmega164P/324P/644P
Asynchronous Clock Recovery
Asynchronous Data Recovery
The clock recovery logic synchronizes internal clock to the incoming serial frames.
illustrates the sampling process of the start bit of an incoming frame. The sample rate is 16 times
the baud rate for Normal mode, and eight times the baud rate for Double Speed mode. The hor-
izontal arrows illustrate the synchronization variation due to the sampling process. Note the
larger time variation when using the Double Speed mode (U2Xn = 1) of operation. Samples
denoted zero are samples done when the RxDn line is idle (i.e., no communication activity).
Figure 17-5. Start Bit Sampling
When the clock recovery logic detects a high (idle) to low (start) transition on the RxDn line, the
start bit detection sequence is initiated. Let sample 1 denote the first zero-sample as shown in
the figure. The clock recovery logic then uses samples 8, 9, and 10 for Normal mode, and sam-
ples 4, 5, and 6 for Double Speed mode (indicated with sample numbers inside boxes on the
figure), to decide if a valid start bit is received. If two or more of these three samples have logical
high levels (the majority wins), the start bit is rejected as a noise spike and the Receiver starts
looking for the next high to low-transition. If however, a valid start bit is detected, the clock recov-
ery logic is synchronized and the data recovery can begin. The synchronization process is
repeated for each start bit.
When the receiver clock is synchronized to the start bit, the data recovery can begin. The data
recovery unit uses a state machine that has 16 states for each bit in Normal mode and eight
states for each bit in Double Speed mode.
the parity bit. Each of the samples is given a number that is equal to the state of the recovery
unit.
Figure 17-6. Sampling of Data and Parity Bit
The decision of the logic level of the received bit is taken by doing a majority voting of the logic
value to the three samples in the center of the received bit. The center samples are emphasized
on the figure by having the sample number inside boxes. The majority voting process is done as
follows: If two or all three samples have high levels, the received bit is registered to be a logic 1.
If two or all three samples have low levels, the received bit is registered to be a logic 0. This
majority voting process acts as a low pass filter for the incoming signal on the RxDn pin.
(U2X = 0)
(U2X = 1)
Sample
Sample
(U2X = 0)
(U2X = 1)
Sample
Sample
RxD
RxD
0
0
IDLE
0
1
1
1
1
2
2
3
2
3
2
4
4
5
3
5
3
6
6
Figure 17-6
7
4
7
4
8
8
START
BIT n
9
5
9
5
10
10
shows the sampling of the data bits and
11
11
6
6
12
12
13
13
7
7
14
14
15
15
8
8
16
16
1
1
1
1
7674F–AVR–09/09
2
BIT 0
Figure 17-5
3
2