ATMEGA644P-A15MZ Atmel, ATMEGA644P-A15MZ Datasheet - Page 88

• Manufacturer Part Number: ATMEGA644P-A15MZ
• Description: MCU AVR 64KB FLASH 16MHZ 44QFN
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA644P-A15MZ

• Package / Case: 44-VQFN Exposed Pad
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Speed: 16MHz
• Number Of I /o: 32
• Eeprom Size: 2K x 8
• Core Processor: AVR
• Program Memory Type: FLASH
• Ram Size: 4K x 8
• Program Memory Size: 64KB (64K x 8)
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Connectivity: I²C, SPI, UART/USART
• Core Size: 8-Bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

88
ATmega164P/324P/644P
• INT0/RXD1/PCINT26 – Port D, Bit 2
INT0, External Interrupt source 0. The PD2 pin can serve as an external interrupt source to the
MCU.
RXD1, RXD0, Receive Data (Data input pin for the USART1). When the USART1 receiver is
enabled this pin is configured as an input regardless of the value of DDD2. When the USART
forces this pin to be an input, the pull-up can still be controlled by the PORTD2 bit.
PCINT26, Pin Change Interrupt Source 26: The PD2 pin can serve as an external interrupt
source.
• TXD0/PCINT25 – Port D, Bit 1
TXD0, Transmit Data (Data output pin for the USART0). When the USART0 Transmitter is
enabled, this pin is configured as an output regardless of the value of DDD1.
PCINT25, Pin Change Interrupt Source 25: The PD1 pin can serve as an external interrupt
source.
• RXD0/PCINT24 – Port D, Bit 0
RXD0, Receive Data (Data input pin for the USART0). When the USART0 receiver is enabled
this pin is configured as an input regardless of the value of DDD0. When the USART forces this
pin to be an input, the pull-up can still be controlled by the PORTD0 bit.
PCINT24, Pin Change Interrupt Source 24: The PD0 pin can serve as an external interrupt
source.
Table 12-13 on page 88
the overriding signals shown in
Table 12-13. Overriding Signals for Alternate Functions PD7:PD4
Signal Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
PD7/OC2A/
PCINT31
0
0
0
0
OC2A ENABLE
OCA2A
PCINT31 • PCIE3
1
PCINT31 INPUT
–
and
Table 12-14 on page 89
Figure 12-5 on page
PD6/ICP1/
OC2B/
PCINT30
0
0
0
0
OC2B ENABLE
PCINT30 • PCIE3
1
ICP1 INPUT
PCINT30 INPUT
–
OC2B
77.
relates the alternate functions of Port D to
PD5/OC1A/
PCINT29
0
0
0
0
OC1A ENABLE
OC1A
PCINT29 • PCIE3
1
PCINT29 INPUT
–
PD4/OC1B/XCK1/
PCINT28
0
0
0
0
OC1B ENABLE
OC1B
PCINT28 • PCIE3
1
PCINT28 INPUT
–
7674F–AVR–09/09