ST10F276Z5Q3TR STMicroelectronics, ST10F276Z5Q3TR Datasheet - Page 129

• Manufacturer Part Number: ST10F276Z5Q3TR
• Description: MCU 16BIT 832KBIT FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276Z5Q3TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 64MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Interface Type: CAN, I2C
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• For Use With: 497-6399 - KIT DEV STARTER ST10F276Z5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

ST10F276Z5
19.9
Table 62.
(Synchronous)
Hardware Reset
Power-on Reset
(Asynchronous)
Short Hardware
Long Hardware
(Synchronous)
Event
Reset
Reset
Reset summary
A summary of the different reset events is reported in the table below.
Reset event
(1)
0
0
1
x
0
0
0
0
1
1
1
1
1
1
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
x
x
N Asynch.
N Asynch.
N Asynch.
N Asynch.
N Synch.
N Synch.
N Synch.
N Synch.
Y
Y Asynch.
Y Asynch.
Y Synch.
Y Synch.
Y Synch.
Y Synch.
x
max (4 TCL, 500 ns)
max (4 TCL, 500 ns)
max (4 TCL, 500 ns)
max (4 TCL, 500 ns)
max(4 TCL, 500 ns)
max(4 TCL, 500 ns)
max(4 TCL, 500 ns)
max(4 TCL, 500 ns)
Activated by internal logic only for 1024 TCL
Activated by internal logic only for 1024 TCL
1032 + 12 TCL +
1032 + 12 TCL +
1032 + 12 TCL +
1032 + 12 TCL +
(Reson. + PLL)
(Crystal + PLL)
Activated by internal logic for 1024 TCL
Activated by internal logic for 1024 TCL
1 ms (VREG)
1 ms (VREG)
10.2 ms
1.2 ms
500 ns
500 ns
500 ns
500 ns
min
NOT APPLICABLE
RSTIN
FORBIDDEN
max(4 TCL, 500 ns)
max(4 TCL, 500ns)
max(4 TCL, 500ns)
max(4 TCL, 500ns)
1032 + 12 TCL +
1032 + 12 TCL +
1032 + 12 TCL +
1032 + 12 TCL +
max
-
-
-
-
-
-
-
-
-
-
1
0
0
0
0
0
0
1
0
0
0
0
0
0
WDTCON Flags
1
1
1
1
1
1
0
0
0
0
1
1
1
1
System reset
1
1
1
1
1
1
1
1
1
1
1
1
1
1
129/239
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0