ST10F276Z5Q3TR STMicroelectronics, ST10F276Z5Q3TR Datasheet - Page 202

• Manufacturer Part Number: ST10F276Z5Q3TR
• Description: MCU 16BIT 832KBIT FLASH 144-PQFP
• Manufacturer: STMicroelectronics
• Series: ST10r

Specifications of ST10F276Z5Q3TR

• Core Processor: ST10
• Core Size: 16-Bit
• Speed: 64MHz
• Connectivity: ASC, CAN, EBI/EMI, I²C, SSC, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 111
• Program Memory Size: 832KB (832K x 8)
• Program Memory Type: FLASH
• Ram Size: 68K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 24x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 144-QFP
• Processor Series: ST10F27x
• Core: ST10
• Data Bus Width: 16 bit
• Data Ram Size: 68 KB
• Interface Type: CAN, I2C
• Maximum Clock Frequency: 64 MHz
• Number Of Programmable I/os: 111
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 24 Channel
• For Use With: 497-6399 - KIT DEV STARTER ST10F276Z5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Electrical characteristics
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periods within the considered time interval.
On the contrary, assuming again a noiseless PLL input and supposing that the VCO is
dominated by its 1/f
where N is the number of clock periods within the considered time interval.
The jitter in the PLL loop can be modelized as dominated by the i1/f
than a certain value depending on the PLL output frequency and on the bandwidth
characteristics of loop. Above this first value, the jitter becomes dominated by the i1/f
component. Lastly, for N greater than a second value of N, a saturation effect is evident, so
the jitter does not grow anymore when considering a longer time interval (jitter stable
increasing the number of clock periods N). The PLL loop acts as a high pass filter for any
noise in the loop, with cutoff frequency equal to the bandwidth of the PLL. The saturation
value corresponds to what has been called self referred long term jitter of the PLL. In
Figure 56
CPU frequencies) is shown: The curves represent the very worst case, computed taking into
account all corners of temperature, power supply and process variations; the real jitter is
always measured well below the given worst case values.
Noise in supply and substrate
Digital supply noise adds determining elements to PLL output jitter, independent of the
multiplication factor. Its effect is strongly reduced thanks to particular care used in the
physical implementation and integration of the PLL module inside the device. In any case,
the contribution of digital noise to global jitter is widely taken into account in the curves
provided in
Figure 53. ST10F276Z5 PLL jitter
the maximum jitter trend versus the number of clock periods N (for some typical
Figure
T
±5
±4
±3
±2
±1
JIT
0
0
56.
3
noise, the R.M.S. value of the accumulated jitter is proportional to N,
200
16 MHz
400
24 MHz
N (CPU clock periods)
600
32 MHz
40 MHz
800
1000
2
1200
noise for N smaller
64 MHz
1400
ST10F276Z5
3
noise