MC908JL16CDWE Freescale Semiconductor, MC908JL16CDWE Datasheet - Page 94

IC MCU 16K FLASH 8MHZ 28-SOIC

MC908JL16CDWE

Manufacturer Part Number
MC908JL16CDWE
Description
IC MCU 16K FLASH 8MHZ 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet

Specifications of MC908JL16CDWE

Core Processor
HC08
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI
Peripherals
LED, LVD, POR, PWM
Number Of I /o
23
Program Memory Size
16KB (16K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SOIC (7.5mm Width)
Controller Family/series
HC08
No. Of I/o's
23
Ram Memory Size
512Byte
Cpu Speed
8MHz
No. Of Timers
2
Embedded Interface Type
I2C, SCI
Rohs Compliant
Yes
Processor Series
HC08JL
Core
HC08
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SCI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
23
Number Of Timers
4
Operating Supply Voltage
2.7 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908JL16E, M68CBL05CE
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 12 Channel
For Use With
DEMO908JL16E - BOARD DEMO FOR MC908JL16
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details

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Serial Communications Interface (SCI)
7.4.3.5 Baud Rate Tolerance
A transmitting device may be operating at a baud rate below or above the receiver baud rate.
Accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the
actual stop bit. Then a noise error occurs. If more than one of the samples is outside the stop bit, a framing
error occurs. In most applications, the baud rate tolerance is much more than the degree of misalignment
that is likely to occur.
As the receiver samples an incoming character, it resynchronizes the RT clock on any valid falling edge
within the character. Resynchronization within characters corrects misalignments between transmitter bit
times and receiver bit times.
Slow Data Tolerance
Figure 7-7
or a framing error. The slow stop bit begins at RT8 instead of RT1 but arrives in time for the stop bit data
samples at RT8, RT9, and RT10.
For an 8-bit character, data sampling of the stop bit takes the receiver
9 bit times × 16 RT cycles + 10 RT cycles = 154 RT cycles.
With the misaligned character shown in
the count of the transmitting device is
9 bit times × 16 RT cycles + 3 RT cycles = 147 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 8-bit
character with no errors is
For a 9-bit character, data sampling of the stop bit takes the receiver
10 bit times × 16 RT cycles + 10 RT cycles = 170 RT cycles.
With the misaligned character shown in
the count of the transmitting device is
10 bit times × 16 RT cycles + 3 RT cycles = 163 RT cycles.
The maximum percent difference between the receiver count and the transmitter count of a slow 9-bit
character with no errors is
94
shows how much a slow received character can be misaligned without causing a noise error
RECEIVER
RT CLOCK
MC68HC908JL16 Data Sheet, Rev. 1.1
MSB
170 163
------------------------- -
154 147
------------------------- -
Figure
Figure
Figure 7-7. Slow Data
170
154
7-7, the receiver counts 154 RT cycles at the point when
7-7, the receiver counts 170 RT cycles at the point when
×
×
100
100
SAMPLES
=
=
DATA
4.12%
4.54%
STOP
Freescale Semiconductor

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