C8051F067-GQ Silicon Laboratories Inc, C8051F067-GQ Datasheet - Page 77

• Manufacturer Part Number: C8051F067-GQ
• Description: IC 8051 MCU 32K FLASH 64TQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F06xr

Specifications of C8051F067-GQ

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 32KB (32K x 8)
• Program Memory Type: FLASH
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 2x16b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: C8051F0x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C, SMBus, SPI, UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 24
• Number Of Timers: 5
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F060DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 16 bit, 1 Channel
• On-chip Dac: 12 bit, 2 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 336-1222

Pointer Registers are initialized to the values contained in the DMA Data Address Beginning Registers
(DMA0DAH and DMA0DAL). The Data Address Pointer Registers are automatically incremented by 2 or 4
after each data write by the DMA interface.
6.4.
When the DMA interface begins an operation cycle, the DMA Instruction Status Register (DMA0ISW,
Figure 6.9) is loaded with the address contained in the DMA Instruction Boundary Register (DMA0BND,
Figure 6.8). The instruction is fetched from the Instruction Buffer, and the DMA Control Logic waits for data
from the appropriate ADC(s). The DMA will execute each instruction once, and then increment DMA0ISW
to the next instruction address. When the current DMA instruction is an End of Operation instruction, the
Instruction Status Register is reset to the Instruction Boundary Register. If the Continuous Conversion bit
(bit 7, CCNV) in the End of Operation instruction word is set to ‘1’, the Repeat Counter is ignored, and the
DMA will continue to execute instructions indefinitely. When CCNV is set to ‘0’, the Repeat Counter (regis-
ters DMA0CSH and DMA0CSL) is decremented, and the DMA will continue to execute instructions until
the Repeat Counter reaches 0x0000. The Repeat Counter is initialized with the Repeat Counter Limit
value (registers DMA0CTH and DMA0CTL) at the beginning of the DMA operation. An example of Mode 0
operation is shown in Figure 6.2.
DMA0BND
Instruction Execution in Mode 0
0x3F
0x03
0x02
0x01
0x00
...
INSTRUCTION
(64 Bytes)
BUFFER
00000000
00110000
01000000
00010000
Figure 6.2. DMA Mode 0 Operation
Rev. 1.2
C8051F060/1/2/3/4/5/6/7
ADC0H (Diff.)
ADC0H (Diff.)
ADC0L (Diff.)
XRAM
ADC1H
ADC0H
ADC1H
ADC0H
ADC0H
ADC1L
ADC0L
ADC0L
ADC1L
ADC0L
ADC0L
DMA0CSH:L = 0x0000
DMA0CSH:L = DMA0CTH:L - 1
DMA0CSH:L = DMA0CTH:L
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