PIC16C74-04I/P Microchip Technology, PIC16C74-04I/P Datasheet - Page 24

• Manufacturer Part Number: PIC16C74-04I/P
• Description: MICRO CTRL 4K 4MHZ OTP 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C74-04I/P

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Size: 7KB (4K x 14)
• Program Memory Type: OTP
• Ram Size: 192 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 8x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -

PIC16C7X
TABLE 4-1:
DS30390E-page 24
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as '0'.
Note 1: These registers can be addressed from either bank.
Address Name
Bank 1
(1)
(1)
(1)
(1)
(1,2)
(1)
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC16C72, always maintain these bits clear.
INDF
OPTION
PCL
STATUS
FSR
TRISA
TRISB
TRISC
PCLATH
INTCON
PIE1
PCON
PR2
SSPADD
SSPSTAT
ADCON1
Shaded locations are unimplemented, read as ‘0’.
contents are transferred to the upper byte of the program counter.
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PIC16C72 SPECIAL FUNCTION REGISTER SUMMARY (Cont.’d)
Addressing this location uses contents of FSR to address data memory (not a physical register)
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
PORTB Data Direction Register
PORTC Data Direction Register
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Timer2 Period Register
Synchronous Serial Port (I
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
RBPU
IRP
Bit 7
GIE
—
—
—
—
—
—
(4)
INTEDG
RP1
ADIE
Bit 6
PEIE
—
—
—
—
—
(4)
PORTA Data Direction Register
2
C mode) Address Register
T0CS
Bit 5
T0IE
RP0
D/A
—
—
—
—
Write Buffer for the upper 5 bits of the PC
T0SE
INTE
Bit 4
TO
—
—
—
P
SSPIE
RBIE
Bit 3
PSA
PD
—
—
S
CCP1IE
PCFG2
Bit 2
T0IF
PS2
R/W
—
Z
TMR2IE
PCFG1
INTF
POR
Bit 1
PS1
DC
UA
TMR1IE
PCFG0
1997 Microchip Technology Inc.
RBIF
BOR
Bit 0
PS0
BF
C
0000 0000 0000 0000
1111 1111 1111 1111
0000 0000 0000 0000
0001 1xxx 000q quuu
xxxx xxxx uuuu uuuu
--11 1111 --11 1111
1111 1111 1111 1111
1111 1111 1111 1111
---0 0000 ---0 0000
0000 000x 0000 000u
-0-- 0000 -0-- 0000
---- --qq ---- --uu
1111 1111 1111 1111
0000 0000 0000 0000
--00 0000 --00 0000
---- -000
Value on:
POR,
BOR
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
other resets
Value on all
---- -000
(3)
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—