PIC17C756-33/SP Microchip Technology, PIC17C756-33/SP Datasheet - Page 179

• Manufacturer Part Number: PIC17C756-33/SP
• Description: MICRO CTRL 16K MEMORY OTP 64SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-33/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: PIC17C756-33/P

17.3
The Watchdog Timer’s function is to recover from
software malfunction. The WDT uses an internal free
running on-chip RC oscillator for its clock source. This
does not require any external components. This RC
oscillator is separate from the RC oscillator of the
OSC1/CLKIN pin. That means that the WDT will run,
even
OSC2/CLKOUT pins have been stopped, for example,
by execution of a SLEEP instruction. During normal
operation and SLEEP mode, a WDT time-out
generates a device RESET. The WDT can be
permanently disabled by programming the configura-
tion bits WDTPS1:WDTPS0 as '00' (Section 17.1).
Under normal operation, the WDT must be cleared on
a regular interval. This time is less the minimum WDT
overflow time. Not clearing the WDT in this time frame
will cause the WDT to overflow and reset the device.
17.3.1
The WDT has a nominal time-out period of 12 ms, (with
postscaler = 1). The time-out periods vary with temper-
ature, V
DC specs). If longer time-out periods are desired, a
postscaler with a division ratio of up to 1:256 can be
assigned to the WDT. Thus, typical time-out periods up
to 3.0 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the postscaler (if assigned to the WDT) and pre-
vent it from timing out thus generating a device RESET
condition.
The TO bit in the CPUSTA register will be cleared upon
a WDT time-out.
FIGURE 17-2: WATCHDOG TIMER BLOCK DIAGRAM
TABLE 17-2:
Address
06h, Unbanked CPUSTA
Legend: - = unimplemented read as '0', q - value depends on condition, shaded cells are not used by the WDT.
Note 1:
Note 1: This oscillator is separate from the external
1997 Microchip Technology Inc.
—
2: This value will be as the device was programmed, or if unprogrammed, will read as all '1's.
if
DD
Watchdog Timer (WDT)
WDT PERIOD
Other (non power-up) resets include: external reset through MCLR and Watchdog Timer Reset.
RC oscillator on the OSC1 pin.
the
and process variations from part to part (see
On-chip RC
Oscillator
Name
Config
clock
REGISTERS/BITS ASSOCIATED WITH THE WATCHDOG TIMER
(1)
on
See Figure 17-1 for location of WDTPSx bits in Configuration Word.
Bit 7
—
WDT Enable
the
WDT
Bit 6
OSC1/CLKIN
—
STKAV
Bit 5
GLINTD
and
Preliminary
Bit 4
Bit 3
TO
17.3.2
The WDT and postscaler are cleared when:
• The device is in the reset state
• A SLEEP instruction is executed
• A CLRWDT instruction is executed
• Wake-up from SLEEP by an interrupt
The WDT counter/postscaler will start counting on the
first edge after the device exits the reset state.
17.3.3
It should also be taken in account that under worst case
conditions (V
WDT postscaler) it may take several seconds before a
WDT time-out occurs.
The WDT and postscaler is the Power-up Timer during
the Power-on Reset sequence.
17.3.4
When the WDT is selected as a normal timer, the clock
source is the device clock. Neither the WDT nor the
postscaler are directly readable or writable. The over-
flow time is 65536 T
is cleared (device is not reset). The CLRWDT instruction
can be used to set the TO bit. This allows the WDT to
be a simple overflow timer. The simple timer does not
increment when in sleep.
Bit 2
PD
CLEARING THE WDT AND POSTSCALER
WDT PROGRAMMING CONSIDERATIONS
WDT AS NORMAL TIMER
4 - to - 1 MUX
WDT Overflow
Postscaler
DD
Bit 1
POR
= Min., Temperature = Max., max.
OSC
cycles. On overflow, the TO bit
Bit 0
BOR
WDTPS1:WDTPS0
--11 1100
Value on
(Note 2)
POR,
BOR
DS30264A-page 179
other resets
Value on all
--11 qq11
(Note 2)
(Note1)