PIC17C756-33/SP Microchip Technology, PIC17C756-33/SP Datasheet - Page 99

• Manufacturer Part Number: PIC17C756-33/SP
• Description: MICRO CTRL 16K MEMORY OTP 64SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-33/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: PIC17C756-33/P

13.1.3.3
The PWMs will operate regardless of the clock source
of the timer. The use of an external clock has ramifica-
tions that must be understood. Because the external
TCLK12 input is synchronized internally (sampled once
per instruction cycle), the time TCLK12 changes to the
time the timer increments will vary by as much as 1T
(one instruction cycle). This will cause jitter in the duty
cycle as well as the period of the PWM output.
This jitter will be 1T
synchronized with the processor clock. Use of one of
the PWM outputs as the clock source to the TCLK12
input, will supply a synchronized clock.
In general, when using an external clock source for
PWM, its frequency should be much less than the
device frequency (Fosc).
TABLE 13-5:
Address
16h, Bank 3
17h, Bank 3
16h, Bank 7
10h, Bank 2
11h, Bank 2
16h, Bank 1
17h, Bank 1
07h, Unbanked INTSTA
06h, Unbanked CPUSTA
14h, Bank 2
15h, Bank 2
10h, Bank 3
11h, Bank 3
10h, Bank 7
12h, Bank 3
13h, Bank 3
11h, Bank 7
Legend: x = unknown, u = unchanged, - = unimplemented read as '0', q = value depends on conditions,
Note 1: Other (non power-up) resets include: external reset through MCLR and WDT Timer Reset.
1997 Microchip Technology Inc.
shaded cells are not used by PWM Module.
EXTERNAL CLOCK SOURCE
Name
TCON1
TCON2
TCON3
TMR1
TMR2
PIR1
PIE1
PR1
PR2
PW1DCL
PW2DCL
PW3DCL
PW1DCH
PW2DCH
PW3DCH
REGISTERS/BITS ASSOCIATED WITH PWM
CY
, unless the external clock is
Timer1’s register
Timer2’s register
Timer1 period register
Timer2 period register
CA2ED1
CA2OVF
RBIF
RBIE
Bit 7
PEIF
DC1
DC1
DC1
DC9
DC9
DC9
—
—
CA2ED0
CA1OVF
CA4OVF
TMR3IF
TMR3IE
T0CKIF
Bit 6
DC0
DC0
DC0
DC8
DC8
DC8
—
PWM2ON
TM2PW2
TM2PW3
CA1ED1
CA3OVF
TMR2IF
TMR2IE
STKAV
Bit 5
T0IF
DC7
DC7
DC7
—
Preliminary
CY
PWM1ON
CA1ED0
CA4ED1
TMR1IF
TMR1IE
GLINTD
Bit 4
INTF
DC6
DC6
DC6
—
—
—
13.1.3.3.1 MAX RESOLUTION/FREQUENCY FOR
The use of an external clock for the PWM time-base
(Timer1 or Timer2) limits the PWM output to a maxi-
mum resolution of 8-bits. The PWxDCL<7:6> bits must
be kept cleared. Use of any other value will distort the
PWM output. All resolutions are supported when inter-
nal clock mode is selected. The maximum attainable
frequency is also lower. This is a result of the timing
requirements of an external clock input for a timer (see
the Electrical Specification section). The maximum
PWM frequency, when the timers clock source is the
RB4/TCLK12 pin, as shown in Table 13-4 (standard
resolution mode).
CA1/PR3 TMR3ON TMR2ON
CA4ED0
CA2IF
CA2IE
PEIE
Bit 3
DC5
DC5
DC5
T16
TO
—
—
—
TMR3CS TMR2CS
CA3ED1
T0CKIE
CA1IF
CA1IE
EXTERNAL CLOCK INPUT
Bit 2
DC4
DC4
DC4
PD
—
—
—
CA3ED0
TX1IF
TX1IE
Bit 1
T0IE
POR
DC3
DC3
DC3
—
—
—
PWM3ON -000 0000
TMR1ON
TMR1CS
RC1IF
RC1IE
INTE
Bit 0
BOR
DC2
DC2
DC2
—
—
—
DS30264A-page 99
0000 0000
0000 0000
xxxx xxxx
xxxx xxxx
0000 0010
0000 0000
0000 0000
--11 1100
xxxx xxxx
xxxx xxxx
xx-- ----
xx0- ----
xx0- ----
xxxx xxxx
xxxx xxxx
xxxx xxxx
Value on
POR,
BOR
Value on all
0000 0000
0000 0000
-000 0000
uuuu uuuu
uuuu uuuu
0000 0010
0000 0000
0000 0000
--11 qq11
uuuu uuuu
uuuu uuuu
uu-- ----
uu0- ----
uu0- ----
uuuu uuuu
uuuu uuuu
uuuu uuuu
(Note1)
resets
other