PIC17C756-33/SP Microchip Technology, PIC17C756-33/SP Datasheet - Page 268

• Manufacturer Part Number: PIC17C756-33/SP
• Description: MICRO CTRL 16K MEMORY OTP 64SDIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C756-33/SP

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 33MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 50
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: OTP
• Ram Size: 902 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 6 V
• Data Converters: A/D 12x10b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 64-SDIP (0.750", 19.05mm)
• Lead Free Status / RoHS Status: Request inventory verification / Request inventory verification
• Eeprom Size: -
• Other names: PIC17C756-33/P

E.2
There are two address formats. The simplest is the
7-bit address format with a R/W bit (Figure E-2). The
more complex is the 10-bit address with a R/W bit
(Figure E-3). For 10-bit address format, two bytes must
be transmitted with the first five bits specifying this to be
a 10-bit address.
FIGURE E-2:
FIGURE E-3:
E.3
All data must be transmitted per byte, with no limit to
the number of bytes transmitted per data transfer. After
each byte, the slave-receiver generates an acknowl-
edge bit (ACK) (Figure E-4). When a slave-receiver
doesn’t acknowledge the slave address or received
data, the master must abort the transfer. The slave
must leave SDA high so that the master can generate
the STOP condition (Figure E-1).
FIGURE E-5:
DS30264A-page 268
S
R/W
ACK
S 1 1 1 1 0 A9 A8 R/W ACK A7 A6 A5 A4 A3 A2 A1 A0 ACK
ACK
S
R/W
- Start Condition
- Read/Write Pulse
- Acknowledge
SDA
SCL
ADDRESSING I
Transfer Acknowledge
Start Condition
Acknowledge
Read/Write pulse
Condition
S
Start
S
MSb
7-BIT ADDRESS FORMAT
I
FORMAT
DATA TRANSFER WAIT STATE
2
C 10-BIT ADDRESS
MSB
slave address
1
2
C DEVICES
Address
2
sent by slave
= 0 for write
acknowledgment
signal from receiver
LSb
R/W ACK
7
Sent by
Slave
R/W
8
Preliminary
ACK
9
byte complete
interrupt with receiver
Wait
State
FIGURE E-4:
If the master is receiving the data (master-receiver), it
generates an acknowledge signal for each received
byte of data, except for the last byte. To signal the end
of data to the slave-transmitter, the master does not
generate an acknowledge (not acknowledge). The
slave then releases the SDA line so the master can
generate the STOP condition. The master can also
generate the STOP condition during the acknowledge
pulse for valid termination of data transfer.
If the slave needs to delay the transmission of the next
byte, holding the SCL line low will force the master into
a wait state. Data transfer continues when the slave
releases the SCL line. This allows the slave to move
the received data or fetch the data it needs to transfer
before allowing the clock to start. This wait state tech-
nique can also be implemented at the bit level,
Figure E-5. The slave will inherently stretch the clock,
when it is a transmitter, but will not when it is a receiver.
The slave will have to clear the CKP bit to enable clock
stretching when it is a receiver.
Transmitter
Output by
Output by
SCL from
Receiver
clock line held low while
interrupts are serviced
Master
1
Data
Data
Condition
Data
Start
2
S
SLAVE-RECEIVER
ACKNOWLEDGE
3 8
acknowledgment
signal from receiver
1
ACK
1997 Microchip Technology Inc.
2
not acknowledge
9
acknowledge
Condition
Stop
8
Acknowledgment
P
Clock Pulse for
9