CY8C26643-24AI Cypress Semiconductor Corp, CY8C26643-24AI Datasheet - Page 59

• Manufacturer Part Number: CY8C26643-24AI
• Description: IC MCU 16K FLASH 256B 44LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C26xxxr

Specifications of CY8C26643-24AI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 428-1431; 428-1431-5; 428-1431

9.3.6
Table 58:
Digital Communications Type A 04 Control Register 0
Digital Communications Type A 05 Control Register 0
Digital Communications Type A Block 06 Control Register 0
Digital Communications Type A Block 07 Control Register 0
September 5, 2002
Bit 7 : LSB First
0 = MSB First
1 = LSB First
Bit 6 : Overrun
0 = Indicates that no overrun has taken place
1 = Indicates the RX Data register was overwritten with a new byte before the previous one had been read
Reset when this register is read
Bit 5 : SPI Complete
0 = Indicates the byte is in process of shifting out
1 = Indicates the byte has been shifted out (reset when register is read)
Optional interrupt source for both SPI Master and SPI Slave. Reset when this register is read
Bit 4 : TX Reg Empty
0 = Indicates the TX Data register is not available to accept another byte
1 = Indicates the TX Data register is available to accept another byte
Default interrupt source for SPI Master. Reset when the TX Data Register (Data Register 1) is written.
Bit 3 : RX Reg Full
0 = Indicates the RX Data register is empty
1 = Indicates a byte has been loaded into the RX Data register
Default interrupt source for SPI Slave. Reset when the RX Data Register (Data Register 2) is read
Bit 2 : Clock Phase
0 = Data changes on leading edge and is latched on trailing edge
1 = Data is latched on leading edge and is changed on trailing edge
Bit 1 : Clock Polarity
0 = Non-inverted (clock idle state is low)
1 = Inverted (clock idle state is high)
Bit 0 : Enable
0 = Function Disabled
1 = Function Enabled
Bit Name
Read/
Write
Bit #
POR
Digital Communications Type A Block xx Control Register 0 When Used as SPI Trans-
ceiver
Digital Communications Type A Block xx Control Register 0...
LSB First
RW
7
0
Overrun
R
6
0
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
SPI Complete
R
5
0
TX Reg
Empty
R
4
0
(DCA04CR0, Address = Bank 0, 33h)
(DCA05CR0, Address = Bank 0, 37h)
(DCA06CR0, Address = Bank 0, 3Bh)
(DCA07CR0, Address = Bank 0, 3Fh)
RX Reg
Full
R
3
0
Phase
Clock
RW
2
0
Polarity
Clock
RW
Digital PSoC Blocks
1
0
Enable
RW
0
0
59