CY8C26643-24AI Cypress Semiconductor Corp, CY8C26643-24AI Datasheet - Page 65

• Manufacturer Part Number: CY8C26643-24AI
• Description: IC MCU 16K FLASH 256B 44LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C26xxxr

Specifications of CY8C26643-24AI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 428-1431; 428-1431-5; 428-1431

9.5.4.6
A simple linear-feedback shift register, or LFSR, uses an
XOR gate to “add” the values of one or more bits and
feed the result back into the least-significant bit. One
possible realization of a 6-bit LFSR providing a maximal
sequence of 63 six-bit values is shown here:
Denote the first implementation as a (6, 1) LFSR, where
6 gives the length of the output codes and 1 indicates the
tap which feeds the XOR gate along with the final bit.
Then the modular form just shown is denoted as a [6, 5]
LFSR. In general, the equivalent modular form of a sim-
ple N bit LFSR with M taps denoted by (N, t
given by the notation [N, N-t
form (and thus the notation) is determined, the value of
Data Register 1 is easily determined. The bit corre-
sponding to the length and all tap bits are turned on; the
others are zero. Thus, the polynomial specification for
Data Register 1 to implement a [6, 5] LFSR is
00110000b, or 30h. A maximal sequence PRS for 8-bits
giving 255 codes is [8, 4, 3, 2] with polynomial
10001110b or 8Eh.
9.5.4.7
1.
2.
September 5, 2002
Disabled State
When the Control Register Enable bit is set to ‘0’,
the internal block clock is turned off. A write to Data
Register 2 (Seed) is loaded directly into Data Regis-
ter 0 (LFSR) to initialize or reset the seed value. All
outputs are low and the block interrupt is held low.
Reading the LFSR
Figure 13: Polynomial LFSR
+
1
Determining the Polynomial
Usage Notes
1
2
+
3
4
1
2
, N-t
5
2
+
, …, N-t
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
6
3
Figure 14: Polynomial PRS
1
M
, t
]. Once the
+
2
B
, …, t
4
M
) is
+
The PRS function utilizes a different “modular” architec-
ture with one XOR gate between each bit of the shift reg-
ister. A maximal sequence equivalent to that produced
by the previous realization is generated by the following
modular LFSR
9.5.5
9.5.5.1
The CRC uses a shift register and XOR gates like the
PRS function. However, instead of an output bit stream,
the CRC function expects an input bit stream. Function-
ally the CRC block is identical to the PRS with the excep-
tion of the selected input data. Input data must be
presented synchronously to the clock. A polynomial
specification permits the length of the input sequence
over which the cyclic redundancy check computes a
result to be varied. CRC-configured PSoC blocks can be
chained to form longer results.
9.5.5.2
Data Register 0 implements a linear-feedback shift regis-
ter. Data Register 2 holds the “seed” value and when the
block is disabled, a write to Data Register 2 is loaded
5
The current LFSR value can only be read when the
block is disabled by setting the Control Register bit 0
to low. Each byte of the current LFSR value (in the
case of a multi-byte block) must be read individually.
The Data Register 0 byte (LFSR), which returns 0,
then the Data Register 1 byte, which returns the
actual value.
+
CRC - Cyclic Redundancy Check
6
Summary
Registers
+
7
+
8
Digital PSoC Blocks
65