CY8C26643-24AI Cypress Semiconductor Corp, CY8C26643-24AI Datasheet - Page 64

• Manufacturer Part Number: CY8C26643-24AI
• Description: IC MCU 16K FLASH 256B 44LQFP
• Manufacturer: Cypress Semiconductor Corp
• Series: PSOC™ CY8C26xxxr

Specifications of CY8C26643-24AI

• Core Processor: M8C
• Core Size: 8-Bit
• Speed: 24MHz
• Connectivity: SPI, UART/USART
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 40
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.25 V
• Data Converters: A/D 1x8b, 1x11b, 1x12b; D/A 1x9b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Other names: 428-1431; 428-1431-5; 428-1431

2.
3.
4.
5.
9.5.4
9.5.4.1
The PRS function generates an output waveform corre-
sponding to a sequence of pseudo-random numbers. A
linear-feedback shift register generates the sequence
according to a user-specified polynomial. The width of
the numbers in the sequence is variable and the initial
value is determined by a user-defined “seed” value. PRS
64
Enabling
The data input to the Dead-Band function is hard-
ware to the primary output of the previous block,
which is typically programmed to be a PWM. The
proper order for enabling these blocks (writing the
Control Register 0) is PWM first, then Dead-Band.
Disabled State
When the Control Register Enable bit is set to ‘0’,
the internal block clock is turned off. A write to Data
Register 1 (Period) is loaded directly into Data Reg-
ister 0 (Counter) to initialize or reset the dead-band
time. All outputs are low and the block interrupt is
held low.
Asserting the Kill Signal
When the Kill signal is asserted high, both outputs
FO and F1 are held low. When the Kill signal is
selected from an external source through a Global
Input, it is synchronized to the 24 MHz clock and
therefore has up to 42 ns of latency.
Negating the Kill Signal
The Kill signal may be negated at any time. How-
ever, the output may be enabled at an arbitrary time
with respect to the F0 and F1 generation. If exact
timing is required when re-enabling the F0 and F1
outputs, the following procedure is recommended:
1.Kill is asserted.
2.Write to Control Register 0 to disable the
block.
3.Write to Data Register 1 (Deadband time) to
initialize the period.
4.Kill is eventually negated.
5.Write to Control Register 0 to enable the
block.
PRS - Pseudo-Random Sequence
Generator
Summary
Cypress MicroSystems CY8C25122/CY8C26233/CY8C26443/CY8C26643 Family Data Sheet
Document #: 38-12010 CY Rev. ** CMS Rev. 3.20
PSoC blocks can be chained to increase the width of the
numbers and, hence, the length of the sequence. A
chain of N PSoC blocks can generate numbers from 2-
to 8N-bits wide and sequences of up to 2
ues.
9.5.4.2
Data Register 0 implements a linear-feedback shift regis-
ter. Data Register 2 holds the “seed” value and when the
block is disabled, a write to Data Register 2 is loaded
directly into Data Register 0 (The block must be disabled
when writing this value). Data Register 1 specifies the
polynomial and width of the numbers in the sequence
(see 9.5.4.6).
9.5.4.3
The clock input determines the rate at which the output
sequence is produced. The data input must be set to low
for the block to function as a PRS. The multiplexer for
selecting these inputs is controlled by the PSoC block
Input Register (DBA00IN-DCA07IN).
9.5.4.4
The PRS function drives the output serial data stream
synchronous with the input clock. The output bits change
on the rising edge of the input clock. The output may be
driven on the Global Output bus or to the subsequent
digital PSoC block. The PSoC block Output Register
(DBA00OU-DCA07OU) controls output options.
9.5.4.5
The PRS function provides an interrupt based on the
Compare signal between Data Register 0 and Data Reg-
ister 2. Data Register 2 is initially loaded with the “seed”
value, and therefore a periodic interrupt will be gener-
ated when the PRS count matches the seed value.
Registers
Inputs
Outputs
Interrupts
September 5, 2002
8N
-1 distinct val-