MC68HC11F1CPU4 Freescale Semiconductor, MC68HC11F1CPU4 Datasheet - Page 123

• Manufacturer Part Number: MC68HC11F1CPU4
• Description: IC MCU 512 EEPROM 4MHZ 80-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11F1CPU4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

PACTL — Pulse Accumulator Control
Bit 7 — Not implemented
PAEN — Pulse Accumulator System Enable
PAMOD — Pulse Accumulator Mode
PEDGE — Pulse Accumulator Edge Control
Bit 3 — Not implemented
I4/O5 — Input Capture 4/Output Compare 5
RTR[1:0] — RTI Interrupt Rate Selects
9.6.2 Pulse Accumulator Count Register
PACNT — Pulse Accumulator Count
TECHNICAL DATA
RESET:
Always reads zero
This bit has different meanings depending on the state of the PAMOD bit, as shown in
Table 9-6.
Always reads zero
Refer to 9.4 Real-Time Interrupt.
This 8-bit read/write register contains the count of external input events at the PAI in-
put, or the accumulated count. The PACNT is readable even if PAI is not active in gat-
ed time accumulation mode. The counter is not affected by reset and can be read or
written at any time. Counting is synchronized to the internal PH2 clock so that incre-
menting and reading occur during opposite half cycles.
0 = Pulse accumulator disabled
1 = Pulse accumulator enabled
0 = Event counter
1 = Gated time accumulation
0 = Output compare 5 function enable (No IC4)
1 = Input capture 4 function enable (No OC5)
Bit 7
Bit 7
Bit 7
—
0
Table 9-6 Pulse Accumulator Edge Detection Control
PAMOD
PAEN
0
0
1
1
6
0
6
6
Freescale Semiconductor, Inc.
For More Information On This Product,
PAMOD
PEDGE
5
0
5
5
0
1
0
1
Go to: www.freescale.com
TIMING SYSTEM
PEDGE
PAI falling edge increments the counter.
PAI rising edge increments the counter.
A zero on PAI inhibits counting.
A one on PAI inhibits counting.
4
0
4
4
—
0
3
3
3
Action on Clock
I4/O5
2
0
2
2
RTR1
1
0
1
1
RTR0
Bit 0
Bit 0
Bit 0
0
$1026
$1027
9-17