MC68HC11F1CPU4 Freescale Semiconductor, MC68HC11F1CPU4 Datasheet - Page 63

• Manufacturer Part Number: MC68HC11F1CPU4
• Description: IC MCU 512 EEPROM 4MHZ 80-LQFP
• Manufacturer: Freescale Semiconductor
• Series: HC11r

Specifications of MC68HC11F1CPU4

• Core Processor: HC11
• Core Size: 8-Bit
• Speed: 4MHz
• Connectivity: SCI, SPI
• Peripherals: POR, WDT
• Number Of I /o: 30
• Program Memory Type: ROMless
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 4.75 V ~ 5.25 V
• Data Converters: A/D 8x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-LQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Program Memory Size: -

5.1 Resets
5.1.1 Power-On Reset
5.1.2 External Reset (RESET)
TECHNICAL DATA
Resets and interrupt operations load the program counter with a vector that points to
a new location from which instructions are to be fetched. A reset causes the internal
control registers to be initialized to a known state. The program counter is loaded with
a known starting address and execution of instructions begins. An interrupt temporarily
suspends normal program execution while an interrupt service routine is being execut-
ed. After an interrupt has been serviced, the main program resumes as if there had
been no interruption.
There are four possible sources of reset. Power-on reset (POR) and external reset
share the normal reset vector. The computer operating properly (COP) reset and the
clock monitor reset each has its own vector.
A positive transition on V
power-up conditions. POR cannot be used to detect drops in power supply voltages.
A 4064 t
clock generator to stabilize. If RESET is at logical zero at the end of 4064 t
remains in the reset condition until RESET goes to logical one.
It is important to protect the MCU during power transitions. To protect data in EE-
PROM, M68HC11 systems need an external circuit that holds the RESET pin low
whenever V
tector, or other external reset circuits, are the usual source of reset in a system. The
POR circuit only initializes internal circuitry during cold starts. Refer to Figure 2–3.
The CPU distinguishes between internal and external reset conditions by sensing
whether the reset pin rises to a logic one in less than two E-clock cycles after an inter-
nal device releases reset. When a reset condition is sensed, the RESET pin is driven
low by an internal device for four E-clock cycles, then released. Two E-clock cycles
later it is sampled. If the pin is still held low, the CPU assumes that an external reset
has occurred. If the pin is high, it indicates that the reset was initiated internally by ei-
ther the COP system or the clock monitor. It is not advisable to connect an external
resistor capacitor (RC) power-up delay circuit to the reset pin of M68HC11 devices be-
cause the circuit charge time constant can cause the device to misinterpret the type of
reset that occurred.
cyc
DD
(internal clock cycle) delay after the oscillator becomes active allows the
is below the minimum operating level. This external voltage level de-
SECTION 5 RESETS AND INTERRUPTS
Freescale Semiconductor, Inc.
For More Information On This Product,
DD
generates a power-on reset (POR), which is used only for
RESETS AND INTERRUPTS
Go to: www.freescale.com
cyc
, the CPU
5-1