AD6620S/PCB Analog Devices Inc, AD6620S/PCB Datasheet - Page 28

• Manufacturer Part Number: AD6620S/PCB
• Description: BOARD EVAL DUAL RCVR W/AD6620AS
• Manufacturer: Analog Devices Inc

Specifications of AD6620S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6620

AD6620
(0x000–0xFF) RCF Coefficient RAM
Memory that stores user-programmable coefficients for the RCF
filter. The RAM will hold 256 20-bit twos complement words
for a maximum filter length of 256 taps. In Diversity Channel
Real Mode the filter length is limited to 128 taps per channel.
The number of taps used is controlled by N
less of the number of coefficient locations programmed. If filter
size allows, more than one filter can be resident in the memory
at a time. This makes it possible to switch filters without reloading
all of the coefficients.
(0x100–0x1FF) RCF Data RAM
These locations store I and Q data exiting the CIC5 filter stage
while the RCF performs multiply accumulates. The lower 18
bits of the 36-bit location is I data; the upper 18 bits are Q data.
These locations are addressed in memory and are available via
the control ports so that the data RAM can be flushed for test-
ing and simulation purposes. They are not cleared on reset.
(0x300) Mode Control Register
This location brings the chip out of reset and sets the operating
mode. It also specifies how the chip will use its SYNC pins: as
Address
000–0FF
100–1FF
200–27F
300
301
302
303
304
305
306
307
308
309
30A
30B
30C
30D
NOTES
1
2
This bit is set high on RESET. The chip is held into SOFT_RESET until it is written low.
This bit is set low on RESET. This keeps multiple AD6620 SYNC Masters from driving each other.
Bit Width
20
36
0
8
3
32
32
16
8
8
5
8
4
8
8
8
8
Name
RCF Coefficient RAM
RCF Data RAM
Reserved
MODE CONTROL REGISTER
NCO CONTROL REGISTER
NCO SYNC CONTROL REGISTER
NCO_FREQ
NCO PHASE_OFFSET
INPUT/CIC2 SCALE REGISTER
M
CIC5 SCALE REGISTER
M
OUTPUT/RCF CONTROL REGISTER
M
RCF ADDRESS OFFSET REGISTER
N
Reserved (Should Be Written 0)
TAPS
CIC2
CIC5
RCF
– 1
– 1
– 1
– 1
TAPS
Table IX. Control Register and RAM Addresses
–1 (30C) regard-
outputs while acting as a sync master, or as inputs while acting
as a sync slave. This is the only register with a defined power-up
state: on power-up, Bit 0 will be at a Logic “1.” This places the
chip in SOFT_RESET and defines the chip as a sync slave.
Powering up as a sync slave avoids contention problems when
connecting multiple AD6620s.
If Bit 0 is written low and Bits 2 and 1 are low, the AD6620 is in
Single Channel Real Mode. If Bit 1 is high and Bits 0 and 2 are
low, the device is in the Diversity Channel Real Mode. If Bit 2
is high and Bits 0 and 1 are low, the chip is in the Single Chan-
nel Complex Mode. Setting Bit 3 high configures the AD6620
as a SYNC master; the SYNC pins are then used as outputs. If
Bit 3 is low, it is a SYNC slave and the SYNC pins function
as inputs. Bits 7–4 are reserved and should be written low.
(0x301) NCO Control Register
This register allows control of special features of the NCO. If
Bit 0 of this register is high the NCO of the AD6620 is by-passed.
Both the I data and the Q data that are passed through the chip
will be the same and the Spectrum will not be translated. In
bypass the input data is attenuated by 12 dB.
Notation
SYNC_MASK
NCO_FREQ
M
S
M
S
M
RCF
N
CIC5
OUT
TAPS
CIC2
CIC5
RCF
OFF
– 1
– 1
– 1
– 1
Description
RCF Coefficient RAM
RCF Data RAM
Reserved
0: SOFT_RESET
1: Diversity Channel Real Input Mode
2: Single Channel Complex Input Mode
3: Sync Master/Slave
Slave = 0)
7–4: Reserved
0: NCO Bypass (Bypass = 1, Active = 0)
1: Enable Phase Dither
2: Enable Amplitude Dither
7–3: Reserved
Write: Sync Mask Shadow
Read: Sync Mask
Channel Frequency for NCO Tuning
NCO Phase Offset
2–0: S
3: Reserved
4: ExpInv
7–5: : ExpOff
CIC2 Decimation Minus One
4–0: S
7–5: Reserved
CIC5 Decimation Minus One
2–0: Output Scale Factor
3: Unique B Flag (Normal Mode = 0,
Unique B Mode = 1)
7–4: Reserved
RCF Decimation Minus One
Filter Coefficient Address Offset
Number of Taps Minus One
Reserved (Should Be Written 0)
CIC2
CIC5
1
2
(Master = 1,