AD6620S/PCB Analog Devices Inc, AD6620S/PCB Datasheet - Page 5

• Manufacturer Part Number: AD6620S/PCB
• Description: BOARD EVAL DUAL RCVR W/AD6620AS
• Manufacturer: Analog Devices Inc

Specifications of AD6620S/PCB

• Rohs Status: RoHS non-compliant
• Module/board Type: Evaluation Board
• For Use With/related Products: AD6620

TIMING CHARACTERISTICS
Parameter (Conditions)
CLK Timing Requirements:
t
t
t
t
Reset Timing Requirements:
t
Input Data Timing Requirements:
t
t
Parallel Output Switching Characteristics:
t
t
t
t
t
t
t
t
SYNC Timing Requirements:
t
t
SYNC Switching Characteristics:
t
Serial Input Timing:
t
t
t
t
t
Serial Frame Output Timing:
t
t
t
SCLK Switching Characteristics, SBM = “1”:
t
t
t
t
Serial Frame Timing, SBM = “1”:
t
t
SCLK Timing Requirements, SBM = “0”:
t
t
t
NOTES
1
2
3
4
5
Specifications subject to change without notice.
This specification valid for VDD >= 3.3 V. t
Specification pertains to: IN[15:0], EXP[2:0], A/B.
Specification pertains to: SYNC_NCO, SYNC_CIC, SYNC_RCF.
SCLK period will be ≥ 2 × t
SDFS setup and hold time must be met, even when configured as outputs, since internally the signal is sampled at the pad.
CLK
CLK
CLKL
CLKH
RESL
SI
HI
DPR
DPF
DPR
DPF
DPR
DPF
DPR
DPF
SY
HY
DY
SSI
HSI
HSRF
SSF
HSF
DSE
SDFEH
DSO
SCLK
SCLKL
SCLKH
SCLKD
DSF
SDFSH
SCLK
SCLKL
SCLKH
CLK Period
CLK Period
CLK Width Low
CLK Width High
RESET Width Low
Input
Input
CLK to OUT[15:0] Rise Delay
CLK to OUT[15:0] Fall Delay
CLK to DV
CLK to DV
CLK to IQ
CLK to IQ
CLK to AB
CLK to AB
SYNC
SYNC
CLK to SYNC
SDI to SCLKt Setup Time
SDI to SCLKt Hold Time
SDFS to SCLKu Hold Time
SDFS to SCLKt Setup Time
SDFS to SCLKt Hold Time
SCLKu to SDFE Delay Time
SDFE Width High
SCLKu to SDO Delay Time
SCLK Period
SCLK Width Low
SCLK Width High
CLK to SCLK Delay Time
SCLKu to SDFS Delay Time
SDFS Width High
SCLK Period
SCLK Width Low
SCLK Width High
2
2
3
3
to CLK Setup Time
to CLK Hold Time
to CLK Setup Time
to CLK Hold Time
CLK
OUT
OUT
when AD6620 is Serial Bus Master (SBM = 1) depending on the SDIV word.
OUT
OUT
OUT
OUT
4
4
Rise Delay
Fall Delay
Rise Delay
Fall Delay
Rise Delay
Fall Delay
Delay Time
CLKL
and t
(C
LOAD
5
5
CLKH
= 40 pF All Outputs)
still apply.
Temp
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Test
Level
I
I
IV
IV
I
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
V
IV
IV
IV
IV
IV
IV
V
IV
I
V
V
V
IV
V
I
IV
IV
Min
14.93
15.4
7.0
7.0
30.0
–1.0
6.5
8.0
7.5
6.5
5.5
7.0
6.0
7.0
5.5
–1.0
6.5
7.0
1.0
2.0
4.0
1.0
2.0
3.5
4.5
2 × t
6.5
1.0
15.4
0.4 × t
0.4 × t
CLK
1
SCLK
SCLK
AD6620AS
Typ
0.5 × t
0.5 × t
t
0.5 × t
0.5 × t
t
0.5 × t
0.5 × t
SCLK
SCLK
CLK
CLK
SCLK
SCLK
SCLK
SCLK
Max
19.5
19.5
19.0
11.5
19.5
13.5
19.5
13.5
23.5
11.0
11.0
13.0
4.0
AD6620
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns