MCP2030-I/ST Microchip Technology, MCP2030-I/ST Datasheet - Page 38

• Manufacturer Part Number: MCP2030-I/ST
• Description: IC KEYLESS ENTRY AFE 14TSSOP
• Manufacturer: Microchip Technology

Specifications of MCP2030-I/ST

• Rf Type: ISM
• Frequency: 125kHz
• Features: 10kbps
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

MCP2030
TABLE 5-1:
T
demodulator output to the first falling edge. The pulse
width must fall within T
T
demodulator output to the rising edge of the next pulse.
The pulse width must fall within T
T
edge (i.e., the sum of T
and T
0 (Register 5-1), OEH<8:7> is set to ‘00’, then the filter
is disabled. See Figure 2-30 for this case.
The filter will reset, requiring a complete new successive
high and low period to enable LFDATA, under the
following conditions.
• The received high is not greater than the
• During T
• The received low is not greater than the
• The received sequence exceeds the maximum
• A Soft Reset SPI command is received.
DS21981A-page 38
Note 1:
OEH
OEL
OET
configured minimum T
causes a filter Reset.
configured minimum T
T
- T
- or T
- or T
<1:0>
OEH
OET
01
01
01
01
10
10
10
10
11
11
11
11
00
OEL
OEH
is measured from rising edge to the next rising
is measured from the falling edge of the
is measured from the rising edge of the
value:
OEH
OEL
must be t T
+ T
OEH
The timing values of T
minimum and T
temperature and V
oscillator.
> T
> T
<1:0>
OEL
OEL
, a loss of signal for longer than 56 s
00
01
10
11
00
01
10
11
00
01
10
11
XX
OET
OET
> T
OUTPUT ENABLE FILTER
TIMING
OET
OEH
OET
OEH
T
OEH
OEL
(ms)
. If the Configuration Register
OEH
1
1
1
1
2
2
2
2
4
4
4
4
and T
OET
t T
value.
value.
DD
Filter Disabled
is maximum at room
OET
OEL
OEL
= 3.0V, 32 kHz
OEH
.
T
(ms)
). The sum of T
OEL
1
1
2
4
1
1
2
4
1
1
2
4
and T
t
T
OET
OEL
T
(ms)
.
OET
10
3
3
4
6
4
4
5
8
6
6
8
are
OEH
If the filter resets due to a long high-time (T
the high-pulse timer will not begin timing again until
after a gap of T
occurs on the demodulator output.
Disabling the output enable filter disables the T
T
data. See Figure 2-30, Figure 2-31 and Figure 2-32 for
examples.
When viewed from an application perspective, from the
pin input, the actual output enable filter timing must
factor in the analog delays in the input path (such as
demodulator charge and discharge times).
• T
• T
The output enable filter starts immediately after T
the gap after AGC stabilization period.
5.16
The device has typical input sensitivity of 3 mV
means any input signal with amplitude greater than 3
mV
lates the detecting signal amplitude when the input
level is greater than approximately 20 mV
signal amplitude is called “AGC-active level”. The AGC
loop regulates the input voltage so that the input signal
amplitude range will be kept within the linear range of
the detection circuits without saturation. The AGC
Active Status bit (AGCACT<5>) in STATUS Register 7
(Register 5-8) is set if the AGC loop regulates the input
voltage.
Table 5-2 shows the input sensitivity comparison when
the AGCSIG option is used. When AGCSIG option bit is
set, the demodulated output is available only when the
AGC loop is active (see Table 5-1). The channel input
sensitivity can be reduced by setting the appropriate
Configuration registers. Configuration Register 3
(Register 5-4), Configuration Register 4 (Register 5-5)
and Configuration Register 5 (Register 5-6) have the
option to reduce each channel gain from 0 dB to
approximately -30 dB.
OEL
PP
OEH
OEL
requirement and the device passes all detected
can be detected. The internal AGC loop regu-
+ T
- T
Input Sensitivity Control
DR
DR
+ T
- T
E
DF
DF
and another low-to-high transition
© 2005 Microchip Technology Inc.
OEH
PP
> T
OEH
PP
. This
. This
OET
GAP
and
),
,