MCP2030-I/ST Microchip Technology, MCP2030-I/ST Datasheet - Page 42

• Manufacturer Part Number: MCP2030-I/ST
• Description: IC KEYLESS ENTRY AFE 14TSSOP
• Manufacturer: Microchip Technology

Specifications of MCP2030-I/ST

• Rf Type: ISM
• Frequency: 125kHz
• Features: 10kbps
• Package / Case: 14-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

MCP2030
5.22
The device can stay at an ultra low-current mode
(Sleep mode) when it receives a Sleep command via
the Serial Peripheral Interface (SPI). All circuits includ-
ing the RF Limiter, except the minimum circuitry
required to retain register memory and SPI capability,
will be powered down to minimize the current draw.
Power-on Reset or any SPI command, other than the
Sleep command, is required to wake the device from
Sleep.
5.23
The device is in Standby mode when no input signal is
present on the input pins, but is powered and ready to
receive any incoming signals.
5.24
The device is in Low-Current Active mode when an
input signal is present on any input pin and internal
circuitry is switching with the received data.
TABLE 5-4:
DS21981A-page 42
Configuration Register 0
Configuration Register 1
Configuration Register 2
Configuration Register 3
Configuration Register 4
Configuration Register 5
Configuration Register 6
(Column Parity Register)
Register Name
Low-Current Sleep Mode
Low-Current Standby Mode
Low-Current Active Mode
CONFIGURATION REGISTER PARITY BIT EXAMPLE
Bit 8
1
0
0
0
0
1
1
Bit 7
0
0
0
0
0
0
1
Bit 6
1
0
0
0
0
0
0
Bit 5
0
0
0
0
0
0
1
5.25
The Configuration registers are volatile memory.
Therefore, the contents of the registers can be cor-
rupted or cleared by any electrical incidence such as
battery disconnect. To ensure data integrity, the device
has an error detection mechanism using row and col-
umn parity bits of the Configuration register memory
map. The bit 0 of each register is a row parity bit which
is calculated over the eight Configuration bits (from bit
1 to bit 8). The Column Parity Register (Configuration
Register 6) holds column parity bits; each bit is calcu-
lated over the respective columns (Configuration regis-
ters 0 to 5) of the Configuration bits. The STATUS
register is not included for the column parity bit calcula-
tion. Parity is to be odd. The parity bit set or cleared
makes an odd number of set bits. The user needs to
calculate the row and column parity bits using the
contents of the registers and program them. During
operation, the device continuously calculates the row
and column parity bits of the configuration memory
map. If a parity error occurs, the device lowers the
SCLK/ALERT pin (interrupting the microcontroller
section) indicating the configuration memory has been
corrupted or unloaded and needs to be reprogrammed.
At an initial condition after a Power-on Reset, the
values of the registers are all clear (default condition).
Therefore, the device will issue the parity bit error by
lowering the SCLK/ALERT pin. If the user reprograms
the registers with the correct parity bits, the SCLK/
ALERT pin will be toggled to logic high level
immediately.
The parity bit errors do not change or affect any
functional operation.
Table 5-4 shows an example of the register values and
corresponding parity bits.
Bit 4
1
0
0
0
0
0
0
Error Detection of Configuration
Register Data
Bit 3
0
0
0
0
0
0
1
Bit 2
© 2005 Microchip Technology Inc.
0
0
0
0
0
0
1
Bit 1
0
0
0
0
0
0
1
(Row Parity)
Bit 0
0
1
1
1
1
0
1