T48C862M-R3-TNS Atmel, T48C862M-R3-TNS Datasheet - Page 70
T48C862M-R3-TNS
Manufacturer Part Number
T48C862M-R3-TNS
Description
IC MON TIRE PRESS 315MHZ 24SOIC
Manufacturer
Atmel
Datasheet
1.T48C862M-R3-TNS.pdf
(107 pages)
Specifications of T48C862M-R3-TNS
Frequency
315MHz
Modulation Or Protocol
FM, FSK
Data Rate - Maximum
32 kBaud
Power - Output
10dBm
Current - Transmitting
9.5mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Memory Size
1KB EEPROM, 1KB RAM
Voltage - Supply
2 V ~ 4 V
Operating Temperature
-40°C ~ 125°C
Package / Case
24-SOIC (0.200", 5.30mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Applications
-
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9-bit Shift Mode (MCL)
70
T48C862-R3
Figure 66. Example of 8-bit Synchronous Transmit Operation
Figure 67. Example of 8-bit Synchronous Receive Operation
In the 9-bit shift mode, the SSI is able to handle the MCL protocol (described below). It
always operates as an MCL master device, i.e., SC is always generated and output by
the SSI. Both the MCL start and stop conditions are automatically generated whenever
the SSI is activated or deactivated by the SIR-bit. In accordance with the MCL protocol,
the output data is always changed in the clock low phase and shifted in on the high
phase.
(IFN = 0)
(IFN = 1)
Interrupt
Interrupt
SRDY
(IFN = 0)
(IFN = 1)
ACT
Interrupt
Interrupt
SIR
SD
SC
SRDY
ACT
SIR
SD
SC
msb
7 6 5
Write STB
(tx data 1)
rx data 1
4 3 2 1 0
msb
7 6 5 4 3 2 1
tx data 1
lsb
msb
7 6 5
lsb
rx data 2
0
4 3 2 1 0
Write STB
(tx data 2)
lsb
msb
7 6 5 4 3 2 1 0 7 6 5 4 3 2 1
Write STB
(tx data 3)
tx data 2
Read SRB
(rx data 1)
lsb msb
msb
7 6 5 4 3 2 1 0
Read SRB
(rx data 2)
rx data 3
tx data 3
lsb
4554A–4BMCU–02/03
lsb
Read SRB
(rx data 3)
0
7 6 5 4
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