T48C862M-R3-TNS Atmel, T48C862M-R3-TNS Datasheet - Page 84

• Manufacturer Part Number: T48C862M-R3-TNS
• Description: IC MON TIRE PRESS 315MHZ 24SOIC
• Manufacturer: Atmel

Specifications of T48C862M-R3-TNS

• Frequency: 315MHz
• Modulation Or Protocol: FM, FSK
• Data Rate - Maximum: 32 kBaud
• Power - Output: 10dBm
• Current - Transmitting: 9.5mA
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Memory Size: 1KB EEPROM, 1KB RAM
• Voltage - Supply: 2 V ~ 4 V
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 24-SOIC (0.200", 5.30mm Width)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Features: -
• Applications: -

Combination Mode 9:
Biphase Demodulation
84
T48C862-R3
Before activating the demodulator mode the timer and the demodulator stage must be
synchronized with the bitstream. The Manchester code timing consists of parts with the
half bitlength and the complete bitlength. A synchronization routine must start the
demodulator after an interval with the complete bitlength.
The counter can be driven by any internal clock source. The output T3O can be used by
Timer 2 in this mode. The Manchester decoder can also be used for pulse-width demod-
ulation. The input must programmed to detect the positive edge. The demodulator and
timer must be synchronized with the leading edge of the pulse. After that a counter
match with the compare register 1 shifts the state at the input T3I into the shift register.
The next positive edge at the input restarts the timer.
Figure 82. Manchester Demodulation
SSI mode 1:
Timer 3 mode 11: Biphase demodulation with Timer 3
In the Biphase demodulation mode the timer works like in the Manchester demodulation
mode. The difference is that the bits are decoded with the toggle flip-flop. This flip-flop
samples the edge in the middle of the bitframe and the compare register 1 match event
shifts the toggle flip-flop output into shift register. Before activating the demodulation the
timer and the demodulation stage must be synchronized with the bitstream. The
Biphase code timing consists of parts with the half bitlength and the complete bitlength.
The synchronization routine must start the demodulator after an interval with the com-
plete bitlength.
The counter can be driven by any internal clock source and the output T3O can be used
by Timer 2 in this mode.
CM31=SCI
SR-DATA
Timer 3
mode
T3EX
T3I
SI
Synchronize
1
8-bit shift register internal data input (SI) and the internal shift clock
(SCI) from the Timer 3
0
Bit 7
1
1
Bit 6
1
1
Manchester demodulation mode
Bit 5
1
1
0
Bit 4
0
0
Bit 3
0
Bit 2
1
1
4554A–4BMCU–02/03
Bit 1
1
1
Bit 0
0
0