T48C862M-R3-TNS Atmel, T48C862M-R3-TNS Datasheet - Page 75

IC MON TIRE PRESS 315MHZ 24SOIC

T48C862M-R3-TNS

Manufacturer Part Number
T48C862M-R3-TNS
Description
IC MON TIRE PRESS 315MHZ 24SOIC
Manufacturer
Atmel
Datasheet

Specifications of T48C862M-R3-TNS

Frequency
315MHz
Modulation Or Protocol
FM, FSK
Data Rate - Maximum
32 kBaud
Power - Output
10dBm
Current - Transmitting
9.5mA
Data Interface
PCB, Surface Mount
Antenna Connector
PCB, Surface Mount
Memory Size
1KB EEPROM, 1KB RAM
Voltage - Supply
2 V ~ 4 V
Operating Temperature
-40°C ~ 125°C
Package / Case
24-SOIC (0.200", 5.30mm Width)
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Applications
-
Serial Interface Registers
Serial Interface Control
Register 1 (SIC1)
4554A–4BMCU–02/03
Figure 72. SSI Output Masking Function
T1OUT
SYSCL
TOG2
POUT
SIR
SCD
SCS1
SCS0
Bit 3
SIR
In Transmit mode (SDD = 1) shifting starts only if the transmit buffer has been
loaded (SRDY = 1).
Setting SIR-bit loads the contents of the shift register into the receive buffer
(synchronous 8-bit mode only).
In MCL modes, writing a 0 to SIR generates a start condition and writing a 1
generates a stop condition.
SCL
Note: This bit has to be set to "1" during the MCL mode and the Timer 3 mode 10 or 11
/2
SCD
Bit 2
SC
Serial Interface Reset
SIR = 1, SSI inactive
SIR = 0, SSI active
Serial Clock Direction
SCD = 1, SC line used as output
SCD = 0, SC line used as input
Serial Clock source Select bit 1
Serial Clock source Select bit 0
Note: with SCD = 0 the bits SCS1
and SCS0 are insignificant
CL2/1
SCS1
Bit 1
Shift_CL
4-bit counter 2/1
SCS0
Bit 0
Compare 2/1
SO
CM1
MSB
SSI-control
8-bit shift register
SCS1
Auxiliary register address: "9"hex
1
1
0
0
SCS0
1
0
1
0
LSB
T48C862-R3
Control
Timer 2
Internal Clock for SSI
Reset value: 1111b
OMSK
SYSCL/2
T1OUT/2
SI
POUT/2
TOG2/2
Output
SO
75

Related parts for T48C862M-R3-TNS