MFRC52301HN1,157 NXP Semiconductors, MFRC52301HN1,157 Datasheet - Page 31

• Manufacturer Part Number: MFRC52301HN1,157
• Description: IC READER 13.56MHZ 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of MFRC52301HN1,157

• Frequency: 13.56MHz
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Rf Type: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935282956157

NXP Semiconductors
MFRC523_34
Product data sheet
PUBLIC
8.10.1 Reset timing requirements
8.10.2 Oscillator start-up time
8.8.3 Transmitter Power-down mode
8.10 Reset and oscillator start-up time
8.9 Oscillator circuit
for further access to the registers. To ensure this, perform a read access to address 0 until
the MFRC523 answers to the last read command with the register content of address 0.
This indicates that the MFRC523 is ready.
The Transmitter Power-down mode switches off the internal antenna drivers and the RF
field. Transmitter Power-down mode is entered by setting either the TxControlReg
register’s Tx1RFEn bit or Tx2RFEn bit to logic 0.
The clock applied to the MFRC523 provides a time basis for the synchronous system’s
encoder and decoder. The stability of the clock frequency is an important factor for correct
operation. To obtain optimum performance, clock jitter must be reduced as much as
possible. This is best achieved using the internal oscillator buffer with the recommended
circuitry.
If an external clock source is used, the clock signal must be applied to pin OSCIN. In this
case, be very careful in optimizing clock duty cycle and clock jitter. Ensure the clock
quality has been verified.
The reset signal is filtered by a hysteresis circuit and a spike filter before it enters the
digital circuit. The spike filter rejects signals shorter than 10 ns. In order to perform a reset,
the signal must be LOW for at least 100 ns.
If the MFRC523 has been set to a Power-down mode or is powered by a V
start-up time for the MFRC523 depends on the oscillator used and is shown in
The time (t
start-up time is defined by the crystal.
The time (t
before the MFRC523 can be addressed.
Fig 22. Quartz crystal connection
startup
d
) is the internal delay time of the MFRC523 when the clock signal is stable
All information provided in this document is subject to legal disclaimers.
) is the start-up time of the crystal oscillator circuit. The crystal oscillator
Rev. 3.5 — 24 September 2010
115235
OSCOUT
MFRC523
27.12 MHz
OSCIN
001aal162
Contactless reader IC
MFRC523
© NXP B.V. 2010. All rights reserved.
DDX
supply, the
Figure
31 of 97
23.