MFRC52301HN1,157 NXP Semiconductors, MFRC52301HN1,157 Datasheet - Page 92

• Manufacturer Part Number: MFRC52301HN1,157
• Description: IC READER 13.56MHZ 32-HVQFN
• Manufacturer: NXP Semiconductors

Specifications of MFRC52301HN1,157

• Frequency: 13.56MHz
• Package / Case: 32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Features: -
• Rf Type: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 935282956157

NXP Semiconductors
26. Tables
Table 1.
Table 2.
Table 3.
Table 4.
Table 5.
Table 6.
Table 7.
Table 8.
Table 9.
Table 10. BR_T0 and BR_T1 settings . . . . . . . . . . . . . . .12
Table 11. Selectable UART transfer speeds . . . . . . . . . .13
Table 12. UART framing . . . . . . . . . . . . . . . . . . . . . . . . .13
Table 13. Read data byte order . . . . . . . . . . . . . . . . . . . .14
Table 14. Write data byte order . . . . . . . . . . . . . . . . . . . .14
Table 15. Address byte 0 register; address MOSI . . . . . .16
Table 16. Register and bit settings controlling the
Table 17. Register and bit settings controlling the
Table 18. CRC coprocessor parameters . . . . . . . . . . . . .27
Table 19. Interrupt sources . . . . . . . . . . . . . . . . . . . . . . .29
Table 20. Behavior of register bits and their
Table 21. MFRC523 register overview . . . . . . . . . . . . . .33
Table 22. Reserved register (address 00h);
Table 23. Reserved register bit descriptions . . . . . . . . . .36
Table 24. CommandReg register (address 01h);
Table 25. CommandReg register bit descriptions . . . . . .36
Table 26. ComIEnReg register (address 02h);
Table 27. ComIEnReg register bit descriptions . . . . . . . .37
Table 28. DivIEnReg register (address 03h);
Table 29. DivIEnReg register bit descriptions . . . . . . . . .37
Table 30. ComIrqReg register (address 04h);
Table 31. ComIrqReg register bit descriptions . . . . . . . .38
Table 32. DivIrqReg register (address 05h);
Table 33. DivIrqReg register bit descriptions . . . . . . . . . .39
Table 34. Status1Reg register (address 07h);
Table 35. Status1Reg register bit descriptions . . . . . . . .39
Table 36. Status2Reg register (address 08h);
MFRC523_34
Product data sheet
PUBLIC
Quick reference data . . . . . . . . . . . . . . . . . . . . .2
Communication overview for ISO/IEC 14443 A
reader/writer . . . . . . . . . . . . . . . . . . . . . . . . . . .8
Connection protocol for detecting different
interface types . . . . . . . . . . . . . . . . . . . . . . . . .10
signal on pin TX1 . . . . . . . . . . . . . . . . . . . . . . .23
signal on pin TX2 . . . . . . . . . . . . . . . . . . . . . . .24
designation . . . . . . . . . . . . . . . . . . . . . . . . . . .32
reset value: 00h bit allocation . . . . . . . . . . . . .36
reset value: 20h bit allocation . . . . . . . . . . . . .36
reset value: 80h bit allocation . . . . . . . . . . . . .37
reset value: 00h bit allocation . . . . . . . . . . . . .37
reset value: 14h bit allocation . . . . . . . . . . . . .38
reset value: x0h bit allocation . . . . . . . . . . . . .39
reset value: 21h bit allocation . . . . . . . . . . . . .39
Ordering information . . . . . . . . . . . . . . . . . . . . .3
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . .6
MOSI and MISO byte order . . . . . . . . . . . . . . . 11
MOSI and MISO byte order . . . . . . . . . . . . . . . 11
SPI read address . . . . . . . . . . . . . . . . . . . . . . . 11
SPI write address . . . . . . . . . . . . . . . . . . . . . .12
All information provided in this document is subject to legal disclaimers.
Rev. 3.5 — 24 September 2010
115235
Table 37. Status2Reg register bit descriptions . . . . . . . . 40
Table 38. FIFODataReg register (address 09h);
Table 39. FIFODataReg register bit descriptions . . . . . . 41
Table 40. FIFOLevelReg register (address 0Ah);
Table 41. FIFOLevelReg register bit descriptions . . . . . . 41
Table 42. WaterLevelReg register (address 0Bh);
Table 43. WaterLevelReg register bit descriptions . . . . . 42
Table 44. ControlReg register (address 0Ch);
Table 45. ControlReg register bit descriptions . . . . . . . . 42
Table 46. BitFramingReg register (address 0Dh);
Table 47. BitFramingReg register bit descriptions . . . . . 43
Table 48. CollReg register (address 0Eh);
Table 49. CollReg register bit descriptions . . . . . . . . . . . 43
Table 50. Reserved register (address 0Fh);
Table 51. Reserved register bit descriptions . . . . . . . . . . 44
Table 52. Reserved register (address 10h);
Table 53. Reserved register bit descriptions . . . . . . . . . . 44
Table 54. ModeReg register (address 11h);
Table 55. ModeReg register bit descriptions . . . . . . . . . 45
Table 56. TxModeReg register (address 12h);
Table 57. TxModeReg register bit descriptions . . . . . . . 46
Table 58. RxModeReg register (address 13h);
Table 59. RxModeReg register bit descriptions . . . . . . . 46
Table 60. TxControlReg register (address 14h);
Table 61. TxControlReg register bit descriptions . . . . . . 47
Table 62. TxASKReg register (address 15h);
Table 63. TxASKReg register bit descriptions . . . . . . . . 48
Table 64. TxSelReg register (address 16h);
Table 65. TxSelReg register bit descriptions . . . . . . . . . 48
Table 66. RxSelReg register (address 17h);
Table 67. RxSelReg register bit descriptions . . . . . . . . . 49
Table 68. RxThresholdReg register (address 18h);
reset value: 00h bit allocation . . . . . . . . . . . . . 40
reset value: xxh bit allocation . . . . . . . . . . . . . 41
reset value: 00h bit allocation . . . . . . . . . . . . . 41
reset value: 08h bit allocation . . . . . . . . . . . . . 42
reset value: 10h bit allocation . . . . . . . . . . . . . 42
reset value: 00h bit allocation . . . . . . . . . . . . . 43
reset value: xxh bit allocation . . . . . . . . . . . . . 43
reset value: 00h bit allocation . . . . . . . . . . . . . 44
reset value: 00h bit allocation . . . . . . . . . . . . . 44
reset value: 3Fh bit allocation . . . . . . . . . . . . . 45
reset value: 00h bit allocation . . . . . . . . . . . . . 46
reset value: 00h bit allocation . . . . . . . . . . . . . 46
reset value: 80h bit allocation . . . . . . . . . . . . . 47
reset value: 00h bit allocation . . . . . . . . . . . . . 48
reset value: 10h bit allocation . . . . . . . . . . . . . 48
reset value: 84h bit allocation . . . . . . . . . . . . . 49
Contactless reader IC
MFRC523
© NXP B.V. 2010. All rights reserved.
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