DS90UR908QSQE/NOPB National Semiconductor, DS90UR908QSQE/NOPB Datasheet

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DS90UR908QSQE/NOPB

Manufacturer Part Number
DS90UR908QSQE/NOPB
Description
IC DESERIALIZER 65MHZ 48LLP
Manufacturer
National Semiconductor
Datasheet

Specifications of DS90UR908QSQE/NOPB

Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
DS90UR908QSQE/NOPBTR

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© 2010 National Semiconductor Corporation
5 - 65 MHz 24-bit Color FPD-Link II to FPD-Link Converter
General Description
The DS90UR908Q converts FPD-Link II to FPD Link. It trans-
lates a high-speed serialized interface with an embedded
clock over a single pair (FPD-Link II) to four LVDS data/control
streams and one LVDS clock pair (FPD-Link). This serial bus
scheme greatly eases system design by eliminating skew
problems between clock and data, reduces the number of
connector pins, reduces the interconnect size, weight, and
cost, and overall eases PCB layout. In addition, internal DC
balanced decoding is used to support AC-coupled intercon-
nects.
The DS90UR908Q converter recovers the data (RGB) and
control signals and extracts the clock from a serial stream
(FPD-Link II). It is able to lock to the incoming data stream
without the use of a training sequence or special SYNC pat-
terns and does not require a reference clock. A link status
(LOCK) output signal is provided.
Adjustable input equalization of the serial input stream pro-
vides compensation for transmission medium losses of the
cable and reduces the medium-induced deterministic jitter.
EMI is minimized by the use of low voltage differential signal-
ing, output voltage level select feature, and additional output
spread spectrum generation.
With fewer wires to the physical interface of the display, FPD-
Link output with LVDS technology is ideal for high speed, low
power and low EMI data transfer.
The DS90UR908Q is offered in a 48-pin LLP package and is
specified over the automotive AEC-Q100 grade 2 tempera-
ture range of -40˚C to +105˚C.
Applications Diagram
TRI-STATE
®
is a registered trademark of National Semiconductor Corporation.
301051
DS90UR908Q
Features
Applications
5 – 65 MHz support (140 Mbps to 1.82 Gbps Serial Link)
5-channel (4 data + 1 clock) FPD-Link driver outputs
AC Coupled STP Interconnect up to 10 meters in length
Integrated input termination
@ Speed link BIST Mode and reporting pin
Optional I2C compatible Serial Control Bus
RGB888 + VS, HS, DE support
Power down mode minimizes power dissipation
FAST random data lock; no reference clock required
Adjustable input receive equalization
LOCK (real time link status) reporting pin
Low EMI FPD-Link output
SSCG option for lower EMI
1.8V or 3.3V compatible I/O interface
Automotive grade product: AEC-Q100 Grade 2 qualified
>8kV HBM ESD tolerance
Backward compatible mode for operation with older
generation devices
Automotive Display for Navigation
Automotive Display for Entertainment
October 20, 2010
www.national.com
30105127

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DS90UR908QSQE/NOPB Summary of contents

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... The DS90UR908Q is offered in a 48-pin LLP package and is specified over the automotive AEC-Q100 grade 2 tempera- ture range of -40˚C to +105˚C. Applications Diagram TRI-STATE ® registered trademark of National Semiconductor Corporation. © 2010 National Semiconductor Corporation DS90UR908Q Features ■ 5 – 65 MHz support (140 Mbps to 1.82 Gbps Serial Link) ■ ...

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DS90UR908Q Pin Diagram Pin Descriptions Pin Name Pin # I/O, Type FPD-Link II Input Interface RIN LVDS RIN LVDS CMF 42 I, Analog FPD-Link Output Interface TxOUT[3:0]+ 15,19, 21, O, LVDS 23 TxOUT[3:0]- 16,20, 22, O, ...

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Pin Name Pin # I/O, Type LVCMOS Outputs LOCK 27 O, LVMOS Control and Configuration PDB 1 I, LVCMOS w/ pull-down VODSEL 33 I, LVCMOS w/ pull-down OEN 30 I, LVCMOS w/ pull-down OSS_SEL 35 I, LVCMOS w/ pull-down LFMODE ...

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Pin Name Pin # I/O, Type Optional Serial Bus Control Interface SCL 5 I, LVCMOS SDA 4 I/O, LVCMOS Open Drain ID[ Analog Power and Ground VDDL 6, 31 Power VDDA 38, 43 Power VDDP 8 Power VDDSC ...

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Block Diagram Ordering Information NSID Package Description DS90UR908QSQE 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch DS90UR908QSQ 48–pin LLP, 7.0 X 7.0 X 0.8 mm, 0.5 mm pitch DS90UR908QSQX 48–pin LLP, 7.0 X 7.0 X 0.8 mm, ...

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... Absolute Maximum Ratings If Military/Aerospace specified devices are required, please contact the National Semiconductor Sales Office/ Distributors for availability and specifications. Supply Voltage – V (1.8V) DDn Supply Voltage – V (3.3V) DDTX Supply Voltage – V DDIO LVCMOS I/O Voltage −0.3V to +(VDDIO + 0.3V) Receiver Input Voltage LVDS Output Voltage − ...

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Symbol Parameter V High Level Output Voltage OH V Low Level Output Voltage OL I Output Short Circuit Current OS I TRI-STATE ® Output Current OZ 1.8 V I/O LVCMOS DC SPECIFICATIONS – High Level Input Voltage IH ...

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Switching Characteristics Over recommended operating supply and temperature ranges unless otherwise specified. Symbol Parameter FPD-Link II Lock Time t DDLT Figure 6 Input Jitter Tolerance t IJIT Figure 9 FPD-Link Output t Low to High Transition Time TLHT t High ...

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Recommended Timing for the Serial Control Bus Over 3.3V operating supply and temperature ranges unless otherwise specified. Symbol Parameter f SCL Clock Frequency SCL t SCL Low Period LOW t SCL High Period HIGH t Hold time for a start ...

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Note 1: “Absolute Maximum Ratings” indicate limits beyond which damage to the device may occur, including inoperability and degradation of device reliability and/or performance. Functional operation of the device and/or non-degradation at the Absolute Maximum Ratings or other conditions beyond ...

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FIGURE 4. FPD-Link & LVCMOS Powerdown Delay FIGURE 5. FPD-Link Outputs Enable Delay FIGURE 6. PLL Lock Times 11 30105188 30105189 30105114 www.national.com ...

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FIGURE 7. FPD-Link (LVDS) Single-ended and Differential Waveforms www.national.com FIGURE 8. FPD-Link Transmitter Pulse Positions FIGURE 9. Receiver Input Jitter Tolerance 12 30105106 30105117 30105116 ...

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FIGURE 10. BIST PASS Waveform FIGURE 11. Serial Control Bus Timing Diagram 13 30105190 30105136 www.national.com ...

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Functional Description The DS90UR908Q receives 27-bits of data (24-high speed bits and 3 low speed bits) over a single serial FPD-Link II pair operating at 140Mbps to 1.82Gbps. The serial stream con- tains an embedded clock, video control signals and ...

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Video Control Signals are defined as low frequency signals with limited transitions. Glitches of a control signal can cause FIGURE 13. Video Control Signal Filter Wavefrom COLOR BIT MAPPING SELECT The DS90UR908Q can be configured to accept 24-bit color (8-bit ...

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FIGURE 15. 8–bit FPD-LInk Mapping: MSB's on TxOUT3 FPD-LINK II INPUT Common Mode Filter Pin (CMF) — Optional The DS90UR908Q provides access to the center tap of the internal termination. A capacitor may be placed on this pin for additional ...

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INPUTS PDB OEN OSS_SEL LVCMOS 1.8V / 3.3V VDDIO Operation The LVCMOS outputs can operate with 1 3.3 V levels (V ) for target (Display) compatibility. ...

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TABLE 6. SSCG Configuration (LFMODE = H) — Des Output SSC[2:0] Inputs LFMODE = MHz) SSC2 SSC1 FIGURE 16. SSCG ...

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Built In Self Test (BIST) — Optional An optional At-Speed Built In Self Test (BIST) feature sup- ports the testing of the high-speed serial link. This is useful in the prototype stage, equipment production, in-system test and also for system ...

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FIGURE 19. BIST Waveforms 20 30105164 ...

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Serial Bus Control — Optional The DS90UR908Q may also be configured by the use of a serial control bus that is I2C protocol compatible. By default, the I2C reg_0x00'h is set to 00'h and all configuration is set by control/strap ...

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ADD ADD Register Name Bit(s) (dec) (hex Des Config 1 3 Slave ID 6:0 www.national.com FIGURE 22. Serial Control Bus — READ FIGURE 23. Serial Control Bus — WRITE TABLE 8. Serial Bus Control Registers R/W ...

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ADD ADD Register Name Bit(s) (dec) (hex Des Features 5 Des Features 2 7 2:0 R/W Defa Function Description ult (bin) R/W 0 OEN Output Enable Input Table 3 ...

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Applications Information DISPLAY APPLICATION The DS90UR908Q, in conjunction with the DS90UR907Q or DS90UR905Q, is intended for interfacing between a host (graphics processor) and a Display. It supports an 24-bit color depth (RGB888) and up to 1024 X 768 display formats. ...

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POWER UP REQUIREMENTS AND PDB PIN The VDD ( and V supply ramps should be DDn DDTX DDIO faster than 1.5 ms with a monotonic rise. Supplies may power up in any order, however device operation should be ...

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PCB LAYOUT AND POWER SYSTEM CONSIDERATIONS Circuit board layout and stack-up for the LVDS devices should be designed to provide low-noise power feed to the device. Good layout practice will also separate high frequency or high-level inputs and outputs to ...

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Revision History • 03/30/2010 — Initial Release • 07/26/2010 — Update all final AC and DC parameter limits • 08/09/2010 — Update Pin Description of VODSEL 27 www.national.com ...

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Physical Dimensions 48–pin LLP Package (7 7 0.8 mm, 0.5 mm pitch) www.national.com inches (millimeters) unless otherwise noted NS Package Number SQA48A 28 ...

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Notes 29 www.national.com ...

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... For more National Semiconductor product information and proven design tools, visit the following Web sites at: www.national.com Products Amplifiers www.national.com/amplifiers Audio www.national.com/audio Clock and Timing www.national.com/timing Data Converters www.national.com/adc Interface www.national.com/interface LVDS www.national.com/lvds Power Management www.national.com/power Switching Regulators www.national.com/switchers LDOs www.national.com/ldo LED Lighting www ...

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