LFXP3C-3TN100I Lattice, LFXP3C-3TN100I Datasheet - Page 14

FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I

LFXP3C-3TN100I

Manufacturer Part Number
LFXP3C-3TN100I
Description
FPGA - Field Programmable Gate Array 3.1K LUTs 62 IO 1.8/ 2.5/3.3V -3 Spd I
Manufacturer
Lattice
Datasheets

Specifications of LFXP3C-3TN100I

Number Of Programmable I/os
62
Data Ram Size
55296
Supply Voltage (max)
3.465 V
Maximum Operating Temperature
+ 100 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.71 V
Package / Case
TQFP-100
Package
100TQFP
Family Name
LatticeXP
Device Logic Units
3000
Maximum Internal Frequency
320 MHz
Typical Operating Supply Voltage
1.8|2.5|3.3 V
Maximum Number Of User I/os
62
Ram Bits
55296
Re-programmability Support
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
LFXP3C-3TN100I
Manufacturer:
Lattice Semiconductor Corporation
Quantity:
10 000
Architecture
Lattice Semiconductor
LatticeXP Family Data Sheet
For more information on the PLL, please see details of additional technical documentation at the end of this data
sheet.
Dynamic Clock Select (DCS)
The DCS is a global clock buffer with smart multiplexer functions. It takes two independent input clock sources and
outputs a clock signal without any glitches or runt pulses. This is achieved irrespective of where the select signal is
toggled. There are eight DCS blocks per device, located in pairs at the center of each side. Figure 2-12 illustrates
the DCS Block Macro.
Figure 2-12. DCS Block Primitive
CLK0
CLK1
DCS
DCSOUT
SEL
Figure 2-13 shows timing waveforms of the default DCS operating mode. The DCS block can be programmed to
other modes. For more information on the DCS, please see details of additional technical documentation at the end
of this data sheet.
Figure 2-13. DCS Waveforms
CLK0
CLK1
SEL
DCSOUT
sysMEM Memory
The LatticeXP family of devices contain a number of sysMEM Embedded Block RAM (EBR). The EBR consists of
a 9-Kbit RAM, with dedicated input and output registers.
sysMEM Memory Block
The sysMEM block can implement single port, dual port or pseudo dual port memories. Each block can be used in
a variety of depths and widths as shown in Table 2-6.
2-11

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