LFXP3C-3TN144C Lattice, LFXP3C-3TN144C Datasheet - Page 57

• Manufacturer Part Number: LFXP3C-3TN144C
• Description: FPGA - Field Programmable Gate Array 3.1K LUTS 100 I/O
• Manufacturer: Lattice

Specifications of LFXP3C-3TN144C

• Number Of Programmable I/os: 100
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

LatticeXP sysCONFIG Port Timing Specifications
Lattice Semiconductor
sysCONFIG Byte Data Flow
t
t
t
t
t
t
t
t
t
sysCONFIG Byte Slave Clocking
t
t
t
sysCONFIG Serial (Bit) Data Flow
t
t
t
sysCONFIG Serial Slave Clocking
t
t
sysCONFIG POR, Initialization and Wake Up
t
t
t
t
t
t
t
t
t
t
Configuration Master Clock (CCLK)
Frequency
Duty Cycle
1. See Table 2-10 for available CCLK frequencies.
2. The threshold level for PROGRAMN, as well as for CFG[1] and CFG[0], is determined by V
Timing v.F0.11
SUCBDI
HCBDI
CODO
SUCS
HCS
SUWD
HWD
DCB
CORD
BSCH
BSCL
BSCYC
SUSCDI
HSCDI
CODO
SSCH
SSCL
ICFG
VMC
PRGMRJ
PRGM
DINIT
DPPINIT
DINITD
IODISS
IOENSS
MWC
Parameter
2
1
Byte D[0:7] Setup Time to CCLK
Byte D[0:7] Hold Time to CCLK
Clock to Dout in Flowthrough Mode
CS[0:1] Setup Time to CCLK
CS[0:1] Hold Time to CCLK
Write Signal Setup Time to CCLK
Write Signal Hold Time to CCLK
CCLK to BUSY Delay Time
Clock to Out for Read Data
Byte Slave Clock Minimum High Pulse
Byte Slave Clock Minimum Low Pulse
Byte Slave Clock Cycle Time
DI (Data In) Setup Time to CCLK
DI (Data In) Hold Time to CCLK
Clock to Dout in Flowthrough Mode
Serial Slave Clock Minimum High Pulse
Serial Slave Clock Minimum Low Pulse
Minimum Vcc to INIT High
Time from t
Program Pin Pulse Rejection
PROGRAMN Low Time to Start Configuration
INIT Low Time
Delay Time from PROGRAMN Low to INIT Low
Delay Time from PROGRAMN Low to DONE Low
User I/O Disable from PROGRAMN Low
User I/O Enabled Time from CCLK Edge During Wake-up Sequence
Additional Wake Master Clock Signals after Done Pin High
ICFG
to Valid Master Clock
Over Recommended Operating Conditions
Description
3-26
DC and Switching Characteristics
CC
, such that the threshold = V
LatticeXP Family Data Sheet
Selected
Value -
Min.
30%
120
15
—
—
—
—
—
—
—
25
—
—
—
—
—
40
7
3
7
2
7
2
6
8
7
2
6
6
Selected
Value +
Max.
30%
12
12
12
12
50
37
37
25
25
60
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
2
7
1
CC
/2.
cycles
Units
MHz
ms
ms
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
us
ns
ns
ns
ns
ns
ns
%