LFXP3C-3TN144C Lattice, LFXP3C-3TN144C Datasheet - Page 71

• Manufacturer Part Number: LFXP3C-3TN144C
• Description: FPGA - Field Programmable Gate Array 3.1K LUTS 100 I/O
• Manufacturer: Lattice

Specifications of LFXP3C-3TN144C

• Number Of Programmable I/os: 100
• Data Ram Size: 55296
• Supply Voltage (max): 3.465 V
• Maximum Operating Temperature: + 90 C
• Minimum Operating Temperature: 0 C
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.71 V
• Package / Case: TQFP-144
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Lattice Semiconductor
LFXP3 & LFXP6 Logic Signal Connections: 144 TQFP (Cont.)
Number
Pin
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
93
94
95
96
97
98
99
Pin Function
VCCAUX
GNDIO2
GNDIO1
GNDIO0
VCCIO2
VCCIO1
VCCIO0
PT25A
PT24A
PT23A
PT22B
PT22A
PT21A
PT20B
PT17A
PT16A
PT15B
PT15A
PT14B
PT13B
PT13A
PT12B
PT12A
PT11B
PT11A
PR9A
PR8B
PR8A
PR7B
PR7A
PR6B
PR5A
PR3B
PR3A
PR2B
PR2A
VCCJ
PT9A
PT8A
PT7A
GND
TDO
TMS
VCC
TCK
TDI
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
Differential
LFXP3
C
C
T
T
T
C
T
C
T
C
T
C
T
C
T
C
T
C
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
RUM0_PLLC_FB_A
RUM0_PLLC_IN_A
RUM0_PLLT_FB_A
RUM0_PLLT_IN_A
Dual Function
PCLKC0_0
PCLKT2_0
PCLKT0_0
VREF1_2
VREF2_2
VREF1_1
VREF2_1
VREF1_0
WRITEN
DOUT
BUSY
CS1N
DQS
DQS
D0
D1
D2
D3
D4
D5
D6
D7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
4-12
Pin Function
VCCAUX
VCCIO2
GNDIO2
VCCIO1
GNDIO1
VCCIO0
GNDIO0
PR12A
PT28A
PT27A
PT26A
PT25B
PT25A
PT24A
PT23B
PT20A
PT19A
PT18B
PT18A
PT17B
PT16B
PT16A
PT15B
PT15A
PT14B
PT14A
PT12A
PT11A
PT10A
PR8B
PR8A
PR7B
PR7A
PR6B
PR5A
PR3B
PR3A
PR2B
PR2A
VCCJ
GND
TDO
TMS
TCK
VCC
TDI
LatticeXP Family Data Sheet
Bank
2
2
2
2
2
2
2
2
2
2
2
2
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
0
0
0
0
0
0
-
-
-
-
-
-
-
-
Differential
LFXP6
C
C
T
T
T
C
T
C
T
C
C
C
C
T
C
T
T
T
T
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
3
3
3
3
Pinout Information
RUM0_PLLC_FB_A
RUM0_PLLC_IN_A
RUM0_PLLT_FB_A
RUM0_PLLT_IN_A
Dual Function
PCLKC0_0
PCLKT2_0
PCLKT0_0
VREF1_2
VREF2_2
VREF1_1
VREF2_1
VREF1_0
WRITEN
DOUT
BUSY
CS1N
DQS
DQS
D0
D1
D2
D3
D4
D5
D6
D7
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-