X28HC64J-12 Intersil, X28HC64J-12 Datasheet - Page 6

• Manufacturer Part Number: X28HC64J-12
• Description: IC EEPROM 64KBIT 120NS 32PLCC
• Manufacturer: Intersil

Specifications of X28HC64J-12

• Format - Memory: EEPROMs - Parallel
• Memory Type: EEPROM
• Memory Size: 64K (8K x 8)
• Speed: 120ns
• Interface: Parallel
• Voltage - Supply: 4.5 V ~ 5.5 V
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 32-LCC (J-Lead)
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Software Data Protection
FIGURE 7. WRITE SEQUENCE FOR SOFTWARE DATA
V
CC
WE
PROTECTED STATE
CE
0V
PROTECTION
RE-ENTERS DATA
LAST ADDRESS
WRITE DATA XX
WRITE DATA AA
WRITE DATA A0
WRITE DATA 55
TO ADDRESS
TO ADDRESS
WRITE LAST
TO ADDRESS
AFTER T
ADDRESS
DATA
ADDR
BYTE TO
TO ANY
0AAA
1555
1555
WC
6
1555
AAA
BYTE/PAGE
LOAD ENABLED
OPTIONAL
BYTE/PAGE
LOAD OPERATION
FIGURE 6. TIMING SEQUENCE—BYTE OR PAGE WRITE
0AAA
55
1555
A0
≤t
X28HC64
BLC MAX
Regardless of whether the device has previously been
protected or not, once the software data protection algorithm
is used, the X28HC64 will automatically disable further
writes unless another command is issued to deactivate it. If
no further commands are issued the X28HC64 will be write
protected during power-down and after any subsequent
power-up.
Note: Once initiated, the sequence of write operations
should not be interrupted.
WRITES
PAGE
BYTE
OR
OK
t
WC
WRITE
PROTECTED
(V
CC
)
August 28, 2009
FN8109.2