ISLA118P50IR72EV1Z Intersil, ISLA118P50IR72EV1Z Datasheet - Page 14

• Manufacturer Part Number: ISLA118P50IR72EV1Z
• Description: EVAL BOARD FOR ISLA118P50IR74
• Manufacturer: Intersil

Specifications of ISLA118P50IR72EV1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Theory of Operation
Functional Description
The ISLA118P50 is based upon an 8-bit, 250MSPS A/D
converter core that utilizes a pipelined successive
approximation architecture (Figure 25). The input
voltage is captured by a Sample-Hold Amplifier (SHA)
and converted to a unit of charge. Proprietary
charge-domain techniques are used to successively
compare the input to a series of reference charges.
Decisions made during the successive approximation
operations determine the digital code for each input
value. The converter pipeline requires twelve samples to
produce a result. Digital error correction is also applied,
resulting in a total latency of 17 clock cycles. This is
evident to the user as a latency between the start of a
conversion and the data being available on the digital
outputs.
The device contains two core A/D converters with
carefully matched transfer characteristics. The cores are
clocked on alternate clock edges, resulting in a doubling
of the sample rate.
Time–interleaved A/D systems can exhibit non–ideal
artifacts in the frequency domain if the individual core
A/D characteristics are not well matched. Gain, offset
and timing skew mismatches are of primary concern.
The Intersil Interleave Engine (I2E) performs automatic
interleave calibration for the offset, gain, and sample
time skew mismatch between the core A/Ds. The I2E
circuitry also adjusts in real-time for temperature and
voltage variations.
Residual gain and sample time skew mismatch result in
fundamental image spurs at f
INP
INN
1.25V
14
+
–
SHA
NYQUIST
± f
FIGURE 25. A/D CORE BLOCK DIAGRAM
IN
2.5-BIT
FLASH
. Offset
ISLA118P50
1.5-BIT/STAGE
6-STAGE
mismatches create spurs at DC and multiples of
f
Power-On Calibration
As mentioned previously, the cores perform a
self-calibration at start-up. An internal power-on-reset
(POR) circuit detects the supply voltage ramps and
initiates the calibration when the analog and digital
supply voltages are above a threshold. The following
conditions must be adhered to for the power-on
calibration to execute successfully:
• A frequency-stable conversion clock must be applied
• DNC pins must not be connected
• SDO (pin 66) must be high
• RESETN (pin 25) must begin low
• SPI communications must not be attempted
A user-initiated reset can subsequently be invoked in the
event that the above conditions cannot be met at
power-up.
Pins 3, 4, and SDO require an external 4.7kΩ pull-up to
OVDD. If these pins are pulled low externally during
power-up, calibration will not be executed properly.
After the power supply has stabilized the internal POR
releases RESETN and an internal pull-up pulls it high,
which starts the calibration sequence. If a subsequent
user-initiated reset is desired, the RESETN pin should be
connected to an open-drain driver with a drive strength
in its high impedance state of less than 0.5mA.
The calibration sequence is initiated on the rising edge of
RESETN, as shown in Figure 26. The over-range output
NYQUIST
to the CLKP/CLKN pins
LVDS/LVCMOS
CORRECTION
GENERATION
OUTPUTS
DIGITAL
ERROR
CLOCK
.
1-BIT/STAGE
3-STAGE
FLASH
3-BIT
June 4, 2010
FN7565.1