ISLA118P50IR72EV1Z Intersil, ISLA118P50IR72EV1Z Datasheet - Page 9

• Manufacturer Part Number: ISLA118P50IR72EV1Z
• Description: EVAL BOARD FOR ISLA118P50IR74
• Manufacturer: Intersil

Specifications of ISLA118P50IR72EV1Z

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Switching Specifications
NOTES:
14. The Tri-Level Inputs internal switching thresholds are approximately 0.43V and 1.34V. It is advised to float the inputs, tie to
15. The voltage is expressed in peak-to-peak differential swing. The peak-to-peak singled-ended swing is 1/2 of the differential
16. The relative propagation delay is the timing of the output clock of any A/D with respect to the nominal timing of any other
17. The pipeline latency of this converter is fixed.
18. SPI Interface timing is directly proportional to the A/D sample period (t
19. The SPI may operate asynchronously with respect to the A/D sample clock.
20. The CSB setup time increases in sleep mode due to the reduced power state, CSB setup time in Nap mode is equal to normal
A/D OUTPUT
Aperture Delay
RMS Aperture Jitter
Input Clock to Output Clock
Propagation Delay
Relative Input Clock to Output Clock
Propagation Delay Matching (Note 16)
Input Clock to Data Propagation
Delay, LVDS Mode
Output Clock to Data Propagation
Delay (Note 13)
Synchronous Clock Divider Reset
Setup Time (with respect to the
positive edge of CLKP)
Synchronous Clock Divider Reset Hold
Time (with respect to the positive
edge of CLKP)
Synchronous Clock Divider Reset
Recovery Time
Latency (Pipeline Delay) (Note 17)
Overvoltage Recovery
SPI INTERFACE (Notes 18, 19)
SCLK Period
CSB↓ to SCLK↑ Setup Time
CSB↑ after SCLK↑ Hold Time
Data Valid to SCLK↑ Setup Time
Data Valid after SCLK↑ Hold Time
Data Valid after SCLK↓ Time
Data Invalid after SCLK↑ Time
Sleep Mode CSB↓ to SCLK↑ Setup
Time (Note 20)
ground or AVDD depending on desired function.
swing.
A/D, given that all devices are clocked at the same time and are matched in temperature and voltage. It is specified over the
full operating temperature and voltage range, and is established by characterizaton and not production tested.
mode CSB setup time (4ns min).
PARAMETER
9
AVDD, OVDD = 1.8V, T
AVDD, OVDD = 1.7V to 1.9V,
T
AVDD, OVDD = 1.7V to 1.9V,
T
LVDS or CMOS Mode
DLL recovery time after
Synchronous Reset
Write Operation
Read Operation
Read or Write
Read or Write
Write
Write
Read
Read
Read or Write in Sleep Mode
A
A
= -40°C to +85°C
= -40°C to +85°C
CONDITION
ISLA118P50
A
= 25°C
SYMBOL
t
dt
t
t
SAMPLE
t
RSTRT
t
t
t
t
t
t
RSTH
t
t
RSTS
DSW
DHW
t
t
DHR
CPD
CPD
OVR
DVR
CLK
CLK
t
t
t
j
DC
t
CPD
PD
L
A
H
A
S
S
).
-450
-250
MIN
1.74
300
450
132
150
2.6
2.0
32
11
2
2
8
6
TYP
375
150
2.9
2.6
2.6
90
75
17
0
1
MAX
3.83
450
250
3.3
3.6
52
33
(Note 18)
June 4, 2010
UNITS
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
cycles
FN7565.1
ps
ns
ns
ps
ns
ps
ps
ps
µs
µs
fs