KDC5512-50EVALZ Intersil, KDC5512-50EVALZ Datasheet
KDC5512-50EVALZ
Specifications of KDC5512-50EVALZ
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KDC5512-50EVALZ Summary of contents
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... CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. | 1-888-INTERSIL or 1-888-468-3774 Intersil (and design registered trademark of Intersil Americas Inc. FemtoCharge is a trademark of Kenet Inc. Copyright Intersil Americas Inc. 2008, 2009. All Rights Reserved All other trademarks mentioned are the property of their respective owners. KAD5512P-50 FN6805.3 ...
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... NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and NiPdAu plate - e4 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020. ...
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Table of Contents Pin-Compatible Family . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . ...
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... Minimum Conversion Rate (Note 7) Maximum Conversion Rate 4 KAD5512P-50 Thermal Information Thermal Resistance (Typical, Note QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Operating Temperature . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +150°C Pb-Free Reflow Profile .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp IN SYMBOL CONDITIONS V Differential FS R Differential IN C ...
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Electrical Specifications All specifications apply under the following conditions unless otherwise noted: AVDD = 1.8V, OVDD = 1.8V -40°C to +85°C (typical specifications at +25°C PARAMETER Signal-to-Noise Ratio Signal-to-Noise and Distortion Effective Number of Bits Spurious-Free ...
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Digital Specifications PARAMETER SYMBOL INPUTS Input Current High (SDIO,RESETN) Input Current Low (SDIO,RESETN) Input Voltage High (SDIO, RESETN) Input Voltage Low (SDIO, RESETN) Input Current High (OUTMODE, NAPSLP, CLKDIV, OUTFMT) (Note 8) Input Current Low (OUTMODE, NAPSLP, CLKDIV, OUTFMT) Input ...
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Switching Specifications PARAMETER ADC OUTPUT Aperture Delay RMS Aperture Jitter Output Clock to Data Propagation Delay, LVDS Mode (Note 9) Output Clock to Data Propagation Delay, CMOS Mode (Note 9) Latency (Pipeline Delay) Overvoltage Recovery SPI INTERFACE (Notes 10, 11) ...
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Pinout/Package Information Pin Descriptions PIN # LVDS [LVCMOS] NAME 1, 6, 12, 19, 24, 71 2-5, 13, 14, 17, 18, 28- 11 VINN, VINP 15 16 CLKDIV 20, 21 CLKP, CLKN 22 OUTMODE 23 NAPSLP ...
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Pin Descriptions (Continued) PIN # LVDS [LVCMOS] NAME OUTFMT Exposed Paddle NOTE: LVCMOS Output Mode Functionality is shown in brackets ( ...
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Pinout AVDD 1 DNC 2 3 DNC 4 DNC 5 DNC 6 AVDD 7 AVSS 8 AVSS 9 VINN 10 VINP 11 AVSS 12 AVDD 13 DNC 14 DNC 15 VCM 16 CLKDIV 17 DNC DNC 18 ...
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Typical Performance Curves 90 85 SFDR SNR 200M 400M INPUT FREQUENCY (Hz) FIGURE 3. SNR AND SFDR vs f 100 90 80 SFDRFS (dBFS SNRFS (dBFS) 50 SFDR (dBc) 40 ...
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Typical Performance Curves 450 400 350 300 250 200 150 100 140 200 260 SAMPLE RATE (MSPS) FIGURE 9. POWER vs f SAMPLE 1.0 0.8 0.6 0.4 0.2 0.0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 ...
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Typical Performance Curves -1.0 dBFS IN SNR = 65.4dBFS -20 SFDR = 77.7dBc SINAD = 65.2dBFS -40 -60 -80 -100 -120 0M 50M 100M FREQUENCY (Hz) FIGURE 15. SINGLE-TONE SPECTRUM @ 190MHz -1.0 dBFS ...
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Theory of Operation Functional Description The KAD5512P-50 is based upon a 12-bit, 250MSPS A/D converter core that utilizes a pipelined successive approximation architecture (Figure 20). The input voltage is captured by a Sample-Hold Amplifier (SHA) and converted to a unit ...
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The SDO pin requires an external 4.7kΩ pull-up to OVDD. If the SDO pin is pulled low externally during power-up, calibration will not be executed properly. After the power supply has stabilized the internal POR releases RESETN and an internal ...
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INP 1.0 0.725V 0.6 0.2 FIGURE 24. ANALOG INPUT RANGE Best performance is obtained when the analog inputs are driven differentially. The common-mode output voltage, VCM, should be used to properly bias the inputs as shown in Figures ...
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Jitter In a sampled data system, clock jitter directly impacts the achievable SNR performance. The theoretical relationship between clock jitter (t ) and SNR is shown in Equation 1 and J is illustrated in Figure 29. ⎛ ⎞ 1 ------------------- ...
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In an application where CSB was kept low in sleep mode, the 150µs CSB setup time is not required as the SPI registers are powered on when CSB is low, the chip power dissipation increases by ~ 15mW in this ...
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CSB SCLK SDIO R CSB SCLK SDIO DSW CSB t S SCLK SDIO R DSW CSB t S SCLK SDIO R A12 SDO 19 KAD5512P-50 A12 A11 A10 A1 ...
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CSB SCLK SDIO INSTRUCTION/ADDRESS CSB SCLK SDIO INSTRUCTION/ADDRESS Serial Peripheral Interface A serial peripheral interface (SPI) bus is used to facilitate configuration of the device and to optimize performance. The SPI bus consists of chip select (CSB), serial clock (SCLK) ...
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... A common SPI map, which can accommodate 3 single-channel or multi-channel devices, is used for all 4 or more Intersil ADC products. Certain configuration commands (identified as Indexed in the SPI map) can be executed on a per-converter basis. This register determines which converter is being addressed for an Indexed command important to note that only a single converter can be addressed at a time ...
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The default value of each register will be the result of the self-calibration after initial power-up register incremented or decremented, the user should first read the register value then write the incremented or decremented value ...
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TABLE 12. CLOCK DIVIDER SELECTION VALUE 001 010 100 ADDRESS 0X73: OUTPUT_MODE_A The output_mode_A register controls the physical output format of the data, as well as the logical coding. The KAD5512P-50 can present output data in two physical formats: LVDS ...
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TABLE 16. OUTPUT TEST MODES 0xC0[3:0] OUTPUT TEST VALUE MODE 0101 Reserved 0110 Reserved 0111 One/Zero 1000 User Pattern user_patt1 ADDRESS 0XC2: USER_PATT1_LSB ADDRESS 0XC3: USER_PATT1_MSB These registers define the lower and upper eight bits, respectively, of the first user-defined ...
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SPI Memory Map ADDR PARAMETER BIT 7 (Hex) NAME (MSB) 00 port_config SDO Active 01 reserved 02 burst_end 03-07 reserved 08 chip_id 09 chip_version 10 device_index_A 11-1F reserved 20 offset_coarse 21 offset_fine 22 gain_coarse 23 gain_medium 24 gain_fine 25 modes ...
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ADDR PARAMETER BIT 7 (Hex) NAME (MSB) C0 test_io User Test Mode [1: Single 01 = Alternate 10 = Reserved 11 = Reserved C1 Reserved C2 user_patt 1_lsb B7 C3 user_patt1_msb B15 C4 user_patt 2_lsb B7 C5 user_patt2_msb ...
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... FIGURE 44. LVDS OUTPUTS 0.535V ADC Evaluation Platform Intersil offers an ADC Evaluation platform which can be used to evaluate any of the KADxxxxx ADC family. The platform consists of a FPGA based data capture motherboard and a family of ADC daughtercards. This USB based platform allows a user to quickly evaluate the ADC’s performance at a user’ ...
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Clock Input Considerations Use matched transmission lines to the transformer inputs for the analog input and clock signals. Locate transformers and terminations as close to the chip as possible. Exposed Paddle The exposed paddle must be electrically connected to analog ...
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... Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use ...
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Package Outline Drawing L72.10x10D 72 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE Rev 1, 11/08 10.00 PIN 1 INDEX AREA 6 (4X) 0.15 TOP VIEW 9.80 Sq 6.00 Sq TYPICAL RECOMMENDED LAND PATTERN 30 KAD5512P- 10.00 37 ...