KDC5512-50EVALZ Intersil, KDC5512-50EVALZ Datasheet - Page 21

• Manufacturer Part Number: KDC5512-50EVALZ
• Description: DAUGHTER CARD FOR KDC5512
• Manufacturer: Intersil

Specifications of KDC5512-50EVALZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

transitions to a high state after that point the state machine
will reset and terminate the data transfer.
Figures 36 and 37 illustrate the timing relationships for
2-byte and N-byte transfers, respectively. The operation for a
3-byte transfer can be inferred from these diagrams.
SPI Configuration
ADDRESS 0X00: CHIP_PORT_CONFIG
Bit ordering and SPI reset are controlled by this register. Bit
order can be selected as MSB to LSB (MSB first) or LSB to
MSB (LSB first) to accommodate various microcontrollers.
Bit 7 SDO Active
Bit 6 LSB First
Bit 5 Soft Reset
Bit 4 Reserved
Bits 3:0 These bits should always mirror bits 4:7 to avoid
ambiguity in bit ordering.
ADDRESS 0X02: BURST_END
If a series of sequential registers are to be set, burst mode
can improve throughput by eliminating redundant
addressing. In 3-wire SPI mode the burst is ended by pulling
the CSB pin high. If the device is operated in 2-wire mode
the CSB pin is not available. In that case, setting the
burst_end address determines the end of the transfer.
During a write operation, the user must be cautious to
transmit the correct number of bytes based on the starting
and ending addresses.
Bits 7:0 Burst End Address
Device Information
ADDRESS 0X08: CHIP_ID
ADDRESS 0X09: CHIP_VERSION
The generic die identifier and a revision number,
respectively, can be read from these two registers.
Setting this bit high configures the SPI to interpret serial
data as arriving in LSB to MSB order.
Setting this bit high resets all SPI registers to default
values.
This bit should always be set high.
This register value determines the ending address of the
burst data.
TABLE 6. BYTE TRANSFER SELECTION
[W1:W0]
00
01
10
11
21
BYTES TRANSFERRED
4 or more
1
2
3
KAD5512P-50
Indexed Device Configuration/Control
ADDRESS 0X10: DEVICE_INDEX_A
Bits 1:0 ADC01, ADC00
A common SPI map, which can accommodate
single-channel or multi-channel devices, is used for all
Intersil ADC products. Certain configuration commands
(identified as Indexed in the SPI map) can be executed on a
per-converter basis. This register determines which
converter is being addressed for an Indexed command. It is
important to note that only a single converter can be
addressed at a time.
This register defaults to 00h, indicating that no ADC is
addressed. Error code ‘AD’ is returned if any indexed
register is read from without properly setting
device_index_A.
ADDRESS 0X20: OFFSET_COARSE
ADDRESS 0X21: OFFSET_FINE
The input offset of the ADC core can be adjusted in fine and
coarse steps. Both adjustments are made via an 8-bit word
as detailed in Table 7. The data format is twos complement.
The default value of each register will be the result of the
self-calibration after initial power-up. If a register is to be
incremented or decremented, the user should first read the
register value then write the incremented or decremented
value back to the same register.
ADDRESS 0X22: GAIN_COARSE
ADDRESS 0X23: GAIN_MEDIUM
ADDRESS 0X24: GAIN_FINE
Gain of the ADC core can be adjusted in coarse, medium and
fine steps. Coarse gain is a 4-bit adjustment while medium
and fine are 8-bit. Multiple Coarse Gain Bits can be set for a
total adjustment range of ± 4.2%. (‘0011’ ≅ -4.2% and ‘1100’
≅ +4.2%) It is recommended to use one of the coarse gain
settings (-4.2%, -2.8%, -1.4%, 0, 1.4%, 2.8%, 4.2%) and
fine-tune the gain using the registers at 23h and 24h.
+Full Scale (0xFF)
–Full Scale (0x00)
Nominal Step Size
Determines which ADC is addressed. Valid states for this
register are 0x01 or 0x10. The two ADC cores cannot be
adjusted concurrently.
Mid–Scale (0x80)
PARAMETER
Steps
TABLE 7. OFFSET ADJUSTMENTS
COARSE OFFSET
+133LSB (+47mV)
1.04LSB (0.37mV)
-133LSB (-47mV)
0.0LSB (0.0mV)
0x20[7:0]
255
0.04LSB (0.014mV)
+5LSB (+1.75mV)
-5LSB (-1.75mV)
FINE OFFSET
0x21[7:0]
0.0LSB
255
October 9, 2009
FN6805.3