KDC5512-50EVALZ Intersil, KDC5512-50EVALZ Datasheet - Page 6

• Manufacturer Part Number: KDC5512-50EVALZ
• Description: DAUGHTER CARD FOR KDC5512
• Manufacturer: Intersil

Specifications of KDC5512-50EVALZ

• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Digital Specifications
Timing Diagrams
INPUTS
Input Current High
(SDIO,RESETN)
Input Current Low
(SDIO,RESETN)
Input Voltage High (SDIO,
RESETN)
Input Voltage Low (SDIO,
RESETN)
Input Current High (OUTMODE,
NAPSLP, CLKDIV, OUTFMT)
(Note 8)
Input Current Low (OUTMODE,
NAPSLP, CLKDIV, OUTFMT)
Input Capacitance
LVDS OUTPUTS
Differential Output Voltage
Output Offset Voltage
Output Rise Time
Output Fall Time
CMOS OUTPUTS
Voltage Output High
Voltage Output Low
Output Rise Time
Output Fall Time
CLKOUTN
CLKOUTP
FIGURE 1. LVDS TIMING DIAGRAM (see “Digital Outputs” on
D[11:0]N
D[11:0]P
CLKN
CLKP
INN
INP
PARAMETER
t
CPD
t
SAMPLE N
page 17)
A
t
PD
t
DC
DATA
N-L
LATENCY = L CYCLES
6
DATA
N-L+1
SYMBOL
V
V
V
C
V
V
I
I
V
I
I
t
t
t
t
IH
IH
OS
OH
IL
IL
OL
R
F
R
F
IH
DI
IL
T
DATA
N-L+2
V
V
3mA Mode
3mA Mode
I
I
OH
OL
IN
IN
CONDITIONS
= 1mA
= 1.8V
= 0V
= -500µA
DATA
N
KAD5512P-50
OVDD - 0.3
CLKOUTN
CLKOUTP
FIGURE 2. CMOS TIMING DIAGRAM (“Digital Outputs” on
D[11:0]N
D[11:0]P
1.17
MIN
950
-25
-40
15
0
CLKN
CLKP
INN
INP
t
CPD
t
SAMPLE N
page 17)
A
OVDD - 0.1
TYP
620
965
500
500
-12
0.1
1.8
1.4
25
25
t
1
3
PD
t
DC
DATA
N-L
LATENCY = L CYCLES
DATA
N-L+1
MAX
980
-15
.63
0.3
10
40
-5
DATA
N-L+2
October 9, 2009
UNITS
mV
mV
µA
µA
µA
µA
pF
ps
ps
ns
ns
V
V
V
V
P-P
FN6805.3
DATA
N