CS4228A-KSZ Cirrus Logic Inc, CS4228A-KSZ Datasheet
CS4228A-KSZ
Specifications of CS4228A-KSZ
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CS4228A-KSZ Summary of contents
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Surround Sound Codec Features l Two 24-bit A/D Converters - 102 dB dynamic range - 90 dB THD+N l Six 24-bit D/A Converters - 103 dB dynamic range and SNR - 90 dB THD+N l Sample rates ...
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TABLE OF CONTENTS CHARACTERISTICS AND SPECIFICATIONS ................................................... 4 ANALOG CHARACTERISTICS................................................................... 4 DIGITAL CHARACTERISTICS.................................................................... 6 SWITCHING CHARACTERISTICS ............................................................. 6 SWITCHING CHARACTERISTICS - CONTROL PORT ............................. 8 ABSOLUTE MAXIMUM RATINGS ............................................................ 10 RECOMMENDED OPERATING CONDITIONS ........................................ 10 TYPICAL CONNECTION DIAGRAM ................................................................. 11 ...
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LIST OF FIGURES Figure 1. Serial Audio Port Master Mode Timing ...................................................... 7 Figure 2. Serial Audio Port Slave Mode Timing ........................................................ 7 Figure 3. SPI Control Port Timing ............................................................................. 8 2 Figure Control Port Timing .............................................................................. ...
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CHARACTERISTICS AND SPECIFICATIONS ANALOG CHARACTERISTICS Full Scale Input Sine wave, 1kHz 44.1 kHz BRM, 96 kHz HRM; Measurement Bandwidth kHz; Local components as shown in "Recommended Connection Diagram"; SPI control mode, Left Justified ...
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ANALOG CHARACTERISTICS Parameter Analog Output Characteristics - Minimum Attenuation 100 pF load; unless otherwise specified. DAC Resolution Signal-to-Noise/Idle Channel Noise (DAC muted, A weighted) Dynamic Range (DAC not muted, A weighted) (DAC not muted, unweighted) Total Harmonic ...
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ANALOG CHARACTERISTICS Power Supply Power Supply Current 3.3V Power Supply Rejection (1 kHz DIGITAL CHARACTERISTICS VA =+ 5V) Parameter High-level Input Voltage Low-level Input Voltage High-level Output Voltage ...
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SWITCHING CHARACTERISTICS Parameter RST Low Time SCLK Falling Edge to SDOUT Output Valid LRCK Edge to MSB Valid SDIN Setup Time Before SCLK Rising Edge SDIN Hold Time After SCLK Rising Edge Master Mode SCLK Falling to LRCK Edge SCLK ...
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SWITCHING CHARACTERISTICS - CONTROL PORT VA = +5V; Inputs: logic 0 = DGND, logic 1 = VL+, C Parameter SPI Mode (SDOUT > 47k to GND) CCLK Clock Frequency CS High Time Between Transmissions CS Falling to CCLK Edge CCLK ...
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SWITCHING CHARACTERISTICS - CONTROL PORT VA = +5V; Inputs: logic 0 = DGND, logic 1 = VL, C Parameter 2 ® Mode (SDOUT < 47k to ground) SCL Clock Frequency Bus Free Time Between Transmissions Start Condition Hold ...
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ABSOLUTE MAXIMUM RATINGS Parameter Power Supplies Input Current Analog Input Voltage Digital Input Voltage Ambient Temperature Storage Temperature Notes: 13. Any pin except supplies. Transient currents ±100 mA on the analog input pins will not cause SCR ...
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TYPICAL CONNECTION DIAGRAM Ferrite Bead +5V Supply + 150 + 19 2 100 F 0 150 + 17 2 100 F 0 ...
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FUNCTIONAL DESCRIPTION Overview The CS4228 is a 24-bit audio codec comprised of 2 analog-to-digital converters (ADC) and 6 digital- to-analog converters (DAC), all implemented us- ing single-bit delta-sigma techniques. Other func- tions integrated with the codec include independent digital volume ...
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High frequency noise beyond the audio passband, resulting from the delta-sigma conversion process produces high frequency noise beyond the audio passband, most of which is removed by the on-chip analog filters. The remaining out-of-band noise can be attenuated using an ...
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Clock Generation The master clock, MCLK, is supplied to the CS4228 from an external clock source. If MCLK stops for 10µs, the CS4228 will enter Power Down Mode in which the supply current is reduced as specified under “Power Supply” ...
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LRCK Left Channel SCLK SDIN1/2 SDOUT Right Justified Mode, Data Valid on Rising Edge of SCLK Bits/Sample LRCK SCLK SDIN1/2/3 MSB - SDOUT Left Justified Mode, Data ...
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LRCK SCLK SDIN1/2/3 MSB LSB MSB DAC1 20 clks SDOUT ADCL 20 clks One Line Data Mode, Data Valid on Rising Edge of SCLK Bits/Sample 20 The control port has 2 operating modes: SPI and compatible. In ...
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MAP allows successive reads or writes of consecu- tive registers. Each byte is separated by an ac- knowledge bit. Control Port Bit Definitions All registers are read/write, except the Chip Status register which is read-only. For more detailed in- formation, ...
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The CS4228 will mute the analog outputs, assert the MUTEC pin and enter the Power Down Mode if the supply drops below approximately 4 volts. Power Supply, Layout, and Grounding The CS4228 requires careful attention to power supply and grounding ...
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REGISTER DESCRIPTION All registers are read/write except for Chip Status, which is read only. See the following bit definition tables for bit assignment information. The default bit state after power-up sequence or reset is listed underneath the bit definition for ...
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Chip Control Address 0x02 7 6 DIGPDN RESERVED 1 0 DIGPDN Power down the digital portions of the CODEC 0 - Digital power down Normal operation ADCPDN Power down the analog section of the ADC *0 - Normal ...
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DAC Mute1 Control Address 0x04 7 6 MUT6 MUT5 1 1 MUT6 - MUT1 Mute control for DAC6 - DAC1 respectively. When asserted, the corresponding DAC is digitally attenuated to its maximum value (90.5 dB). When deasserted, the corresponding DAC ...
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DAC De-emphasis Control Address 0x06 7 6 DEMS1 DEMS0 1 0 DEMS1:0 Selects the DAC de-emphasis response curve Reserved 1 - De-emphasis for 48 kHz *2 - De-emphasis for 44.1 kHz 3 - De-emphasis for 32 kHz DEM6 ...
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Serial Port Mode Address 0x0D 7 6 DCK1 DCK0 1 0 DCK1:0 Sets the number of Serial Clocks (SCLK) per Fs period (LRCLK) DCK1 Notes: 1. All formats will default to 16 bits 2. External Slave ...
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PIN DESCRIPTION Serial Audio Data In 3 Serial Audio Data In 2 Serial Audio Data In 1 Serial Audio Data Out Serial Clock Left/Right Clock Digital Ground Digital Power Digital Interface Power Master Clock SCL/CCLK SCL/CCLK SDA/CDIN SDA/CDIN AD0/CS Reset ...
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Serial Clock — SCLK Pin 5, Bidirectional Function: Clocks serial data into the SDIN1, SDIN2, and SDIN3 pins, and out of the SDOUT pin. The pin is an output in master mode, and an input in slave mode. In master ...
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Master Clock - MCLK Pin 10, Input Function: The master clock frequency must be either 128x, 256x, 384x or 512x the input sample rate in Base Rate Mode (BRM) and either 64x, 128x, 192x, or 256x the input sample rate ...
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Mute Control - MUTEC Pin 15, Output Function: The Mute Control pin goes low during the following conditions: power-up initialization, power-down, reset, no master clock present the master clock to left/right clock frequency ratio is incorrect. The Mute ...
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PARAMETER DEFINITIONS Dynamic Range The ratio of the full scale RMS value of the signal to the RMS sum of all other spectral components over the specified bandwidth. Dynamic range is a signal-to-noise measurement over the specified bandwidth made with ...
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PACKAGE DIMENSIONS 28L SSOP PACKAGE DRAWING TOP VIEW DIM Notes: 1. “D” and “E1” are reference datums and do not included mold flash or protrusions, but ...
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