PIC24FJ64GB004-I/ML Microchip Technology, PIC24FJ64GB004-I/ML Datasheet - Page 124

• Manufacturer Part Number: PIC24FJ64GB004-I/ML
• Description: IC, 16BIT MCU, PIC24F, 32MHZ, QFN-44
• Manufacturer: Microchip Technology
• Series: PIC® XLP™ 24Fr

Specifications of PIC24FJ64GB004-I/ML

• Controller Family/series: PIC24
• Ram Memory Size: 8KB
• Cpu Speed: 32MHz
• No. Of Timers: 5
• Interface: I2C, LIN, SPI, UART, USB
• No. Of Pwm Channels: 5
• Core Size: 16 Bit
• Program Memory Size: 64 KB
• Core Processor: PIC
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART, USB OTG
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: FLASH
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-QFN
• Embedded Interface Type: I2C, LIN, SPI, UART, USB
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 876-1004 - PIC24 BREAKOUT BOARD
• Eeprom Size: -
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC24FJ64GB004 FAMILY
REGISTER 9-2:
DS39940D-page 124
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-9
bit 8
bit 7
bit 6-5
bit 4
bit 3
bit 2
bit 1
bit 0
Note 1:
R/W-0, HS
DSFLT
U-0
—
2:
(1)
This bit can only be set while the device is in Deep Sleep mode.
This bit can be set outside of Deep Sleep.
Unimplemented: Read as ‘0’
DSINT0: Interrupt-on-Change bit
1 = External Interrupt 0 was asserted during Deep Sleep
0 = External Interrupt 0 was not asserted during Deep Sleep
DSFLT: Deep Sleep Fault Detected bit
1 = A Fault occurred during Deep Sleep and some Deep Sleep configuration settings may have been
0 = No Fault was detected during Deep Sleep
Unimplemented: Read as ‘0’
DSWDT: Deep Sleep Watchdog Timer Time-out bit
1 = The Deep Sleep Watchdog Timer timed out during Deep Sleep
0 = The Deep Sleep Watchdog Timer did not time out during Deep Sleep
DSRTC: Real-Time Clock and Calendar Alarm bit
1 = The Real-Time Clock and Calendar triggered an alarm during Deep Sleep
0 = The Real-Time Clock and Calendar did not trigger an alarm during Deep Sleep
DSMCLR: Deep Sleep MCLR Event bit
1 = The MCLR pin was asserted during Deep Sleep
0 = The MCLR pin was not asserted during Deep Sleep
Unimplemented: Read as ‘0’
DSPOR: Power-on Reset Event bit
1 = The V
0 = The V
corrupted
U-0
U-0
—
—
DSWAKE: DEEP SLEEP WAKE-UP SOURCE REGISTER
DD
DD
supply POR circuit was active and a POR event was detected
supply POR circuit was not active, or was active, but did not detect a POR event
HS = Hardware Settable bit
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
R/W-0, HS
DSWDT
(1)
U-0
—
(2)
(1)
(1)
(1)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
R/W-0, HS
DSRTC
U-0
(1)
—
(1)
(1)
DSMCLR
R/W-0, HS
U-0
—
(1)
 2010 Microchip Technology Inc.
x = Bit is unknown
U-0
U-0
—
—
R/W-0, HS
R/W-0, HS
DSINT0
DSPOR
bit 8
bit 0
(1)
(2)